公开(公告)号：US6162587A

公开(公告)日：2000-12-19

申请号：US203450

申请日：1998-12-01

申请人： Chih Yuh Yang ,  Christopher F. Lyons ,  Harry J. Levinson ,  Khanh B. Nguyen ,  Fei Wang ,  Scott A. Bell

发明人： Chih Yuh Yang ,  Christopher F. Lyons ,  Harry J. Levinson ,  Khanh B. Nguyen ,  Fei Wang ,  Scott A. Bell

IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/768 ,  G03C5/00

CPC分类号： H01L21/76816 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/32139

摘要： A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a transition metal layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the transition metal layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the transition metal layer. The first etch step includes an etch chemistry that is selective to the transition metal layer over the ultra-thin photoresist layer and the dielectric layer. The transition metal layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.

公开(公告)号：US6140023A

公开(公告)日：2000-10-31

申请号：US203447

申请日：1998-12-01

申请人： Harry J. Levinson ,  Scott A. Bell ,  Christopher F. Lyons ,  Khanh B. Nguyen ,  Fei Wang ,  Chih Yuh Yang

发明人： Harry J. Levinson ,  Scott A. Bell ,  Christopher F. Lyons ,  Khanh B. Nguyen ,  Fei Wang ,  Chih Yuh Yang

IPC分类号： G03F7/075 ,  G03F7/40 ,  G03F9/00

CPC分类号： G03F7/405 ,  G03F7/075 ,  G03F7/40

摘要： A lithographic process for fabricating sub-micron features is provided. A silicon containing ultra-thin photoresist is formed on an underlayer surface to be etched. The ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern. The ultra-thin photoresist is oxidized so as to convert the silicon therein to silicon dioxide. The oxidized ultra-thin photoresist layer is used as a hard mask during an etch step to transfer the pattern to the underlayer. The etch step includes an etch chemistry that is highly selective to the underlayer over the oxidized ultra-thin photoresist layer.

摘要翻译： 提供了用于制造亚微米特征的光刻工艺。 在要蚀刻的底层表面上形成含硅的超薄光致抗蚀剂。 用短波长辐射图案化超薄光致抗蚀剂层以限定图案。 超薄光致抗蚀剂被氧化以将其中的硅转化为二氧化硅。 氧化的超薄光致抗蚀剂层在蚀刻步骤期间用作硬掩模以将图案转印到底层。 蚀刻步骤包括对氧化的超薄光致抗蚀剂层上的底层具有高选择性的蚀刻化学品。

公开(公告)号：US6127070A

公开(公告)日：2000-10-03

申请号：US203283

申请日：1998-12-01

申请人： Chih Yuh Yang ,  Christopher F. Lyons ,  Harry J. Levinson ,  Khanh B. Nguyen ,  Fei Wang ,  Scott A. Bell

发明人： Chih Yuh Yang ,  Christopher F. Lyons ,  Harry J. Levinson ,  Khanh B. Nguyen ,  Fei Wang ,  Scott A. Bell

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L21/302

CPC分类号： H01L21/31144 ,  H01L21/0274 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002

摘要： A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a nitride layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the nitride layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the nitride layer. The first etch step includes an etch chemistry that is selective to the nitride layer over the ultra-thin photoresist layer and the dielectric layer. The nitride layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.

摘要翻译： 提供一种形成通孔结构的方法。 在该方法中，在覆盖第一金属层的抗反射涂层（ARC）层上形成电介质层; 并且在电介质层上形成氮化物层。 在氮化物层上形成超薄光致抗蚀剂层，并用短波长辐射对超薄光致抗蚀剂层进行图案化，以形成通孔图案。 在第一蚀刻步骤期间，将图案化超薄光致抗蚀剂层用作掩模，以将通孔图案转移到氮化物层。 第一蚀刻步骤包括对超薄光致抗蚀剂层和电介质层上的氮化物层有选择性的蚀刻化学品。 在第二蚀刻步骤期间，氮化物层用作硬掩模，以通过蚀刻介电层的部分来形成与通孔图案相对应的接触孔。

公开(公告)号：US6124183A

公开(公告)日：2000-09-26

申请号：US992490

申请日：1997-12-18

申请人： Olov Karlsson ,  Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Larry Wang ,  Effiong Ibok

发明人： Olov Karlsson ,  Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Larry Wang ,  Effiong Ibok

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate using a simplified reverse source/drain planarization mask. Embodiments include forming trenches and refilling them with an insulating material which also covers a main surface of the substrate, polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches, furnace annealing to densify and strengthen the remaining insulating material, masking the insulating material above the large trenches, isotropically etching the insulating material, and polishing to planarize the insulating material. Since the insulating material is partially planarized and strengthened prior to etching, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. Because the features of the planarization mask are relatively few and have a relatively large geometry, the present invention avoids the need to create and implement a critical mask, enabling production costs to be reduced and manufacturing throughput to be increased.

摘要翻译： 使用简化的反向源极/漏极平面化掩模在半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构。 实施例包括形成沟槽并用绝缘材料再填充它们，该绝缘材料也覆盖衬底的主表面，抛光以除去绝缘材料的上部并平面化小沟槽上方的绝缘材料，炉退火致密化并加强其余部分 绝缘材料，掩蔽大沟槽上方的绝缘材料，各向同性地蚀刻绝缘材料，并抛光以使绝缘材料平坦化。 由于在蚀刻之前绝缘材料被部分平坦化和加强，因此可以在仅在大的沟槽上而不是小沟槽形成相对简单的平坦化掩模之后进行蚀刻。 由于平面化掩模的特征相对较少并且具有相对较大的几何形状，因此本发明避免了创建和实施关键掩模的需要，从而能够降低生产成本并提高生产量。

公开(公告)号：US6090712A

公开(公告)日：2000-07-18

申请号：US992489

申请日：1997-12-18

申请人： Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Obok

发明人： Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Obok

IPC分类号： H01L21/762 ,  H01L21/461

CPC分类号： H01L21/76224

摘要： An insulated trench isolation structure is formed in a semiconductor substrate omitting a barrier nitride polish stop layer while avoiding substrate damage, thereby simplifying trench formation and improving planarity. After trench fill, polishing is conducted to effect substantial planarization without exposing the substrate surface, thereby avoiding substrate damage. Etching is then conducted to expose the substrate surface. The omission of the barrier nitride polish stop avoids generation of a topographical step at the substrate/trench fill interface, thereby enhancing the accuracy of subsequent photolithographic techniques in forming features with minimal dimensions.

摘要翻译： 在半导体衬底中形成绝缘沟槽隔离结构，省略了阻挡氮化物抛光停止层，同时避免了衬底损坏，从而简化了沟槽形成并提高了平面度。 在沟槽填充之后，进行抛光以实现基本平坦化而不暴露衬底表面，从而避免衬底损坏。 然后进行蚀刻以暴露衬底表面。 阻挡氮化物抛光停止的省略避免了在衬底/沟槽填充界面处产生形貌步骤，从而在最小尺寸形成特征的同时提高随后的光刻技术的精度。

公开(公告)号：US07427457B1

公开(公告)日：2008-09-23

申请号：US10934277

申请日：2004-09-03

申请人： Marina V. Plat ,  Calvin T. Gabriel ,  Christopher F. Lyons ,  Anna M. Minvielle

发明人： Marina V. Plat ,  Calvin T. Gabriel ,  Christopher F. Lyons ,  Anna M. Minvielle

IPC分类号： G03F9/00

CPC分类号： G03F7/70783 ,  G03F1/44 ,  G03F7/70491 ,  G03F7/70533 ,  G03F7/7065

摘要： The present invention discloses a system and method for designing grating structures for use in situ scatterometry during the photolithography process to detect a photoresist defect (e.g., photoresist erosion, pattern collapse or pattern bending). In one embodiment, a grating structure may be designed with a pitch or critical dimensional smaller than the one used for the semiconductor device. The pitch and the critical dimension of the grating structure may be varied. In another embodiment, the present invention provides for a feedback mechanism between the in situ scatterometry process and the photolithography process to provide an early warning of the existence of a photoresist defect. If a defect is detected on the wafer, the wafer may be sent to be re-worked or re-patterned, thereby avoiding scrapping the entire wafer.

摘要翻译： 本发明公开了一种用于在光刻工艺期间用于原位散射测量的光栅结构的系统和方法，用于检测光致抗蚀剂缺陷（例如，光致抗蚀剂侵蚀，图案崩溃或图案弯曲）。 在一个实施例中，可以设计具有小于用于半导体器件的间距或临界尺寸的光栅结构。 光栅结构的间距和临界尺寸可以变化。 在另一个实施例中，本发明提供了原位散射测量过程和光刻工艺之间的反馈机制，以提供光刻胶缺陷的存在的早期警告。 如果在晶片上检测到缺陷，则可以将晶片发送以进行再加工或重新图案化，从而避免报废整个晶片。

公开(公告)号：US06864556B1

公开(公告)日：2005-03-08

申请号：US10335445

申请日：2002-12-31

申请人： Lu You ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Richard J. Huang ,  Christopher F. Lyons ,  Mark S. Chang ,  Marilyn I. Wright

发明人： Lu You ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Richard J. Huang ,  Christopher F. Lyons ,  Mark S. Chang ,  Marilyn I. Wright

IPC分类号： G03F7/09 ,  H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/47 ,  H01L31/0232

CPC分类号： H01L21/32139 ,  G03F7/091 ,  H01L21/0332 ,  H01L21/28123 ,  H01L29/785

摘要： A bottom anti-reflective coating comprising an organic polymer layer having substantially no nitrogen and a low compressive stress in relation to a polysilicon layer is employed as the lower layer of a bi-layer antireflective coating/hardmask structure to reduce deformation of a pattern to be formed in a patternable layer. The organic polymer layer is substantially transparent to visible radiation, enabling better detection of alignment marks during a semiconductor device fabrication process and improving overlay accuracy. The organic polymer layer provides excellent step coverage and may be advantageously used in the fabrication of structures such as FinFETs.

摘要翻译： 采用底层抗反射涂层，其包含基本上不含氮的有机聚合物层和相对于多晶硅层的低压缩应力作为双层抗反射涂层/硬掩模结构的下层，以减少图案的变形 形成在可图案层中。 有机聚合物层对可见辐射基本上是透明的，能够在半导体器件制造过程中更好地检测对准标记并提高覆盖精度。 有机聚合物层提供优异的台阶覆盖，并且可以有利地用于制造诸如FinFET的结构。

公开(公告)号：US06852455B1

公开(公告)日：2005-02-08

申请号：US10237643

申请日：2002-09-09

申请人： Christopher F. Lyons ,  Cyrus E. Tabery

发明人： Christopher F. Lyons ,  Cyrus E. Tabery

IPC分类号： G03F1/00 ,  G03F1/08 ,  G03F9/00

CPC分类号： G03F1/32 ,  G03F1/54

摘要： An exemplary embodiment relates to a phase shifting mask including a glass substrate layer and an amorphous carbon absorber layer located above the glass substrate layer. The amorphous carbon absorber layer includes apertures through which light passes unaltered to the glass substrate layer.

摘要翻译： 示例性实施例涉及包括玻璃基底层和位于玻璃基底层上方的无定形碳吸收层的相移掩模。 无定形碳吸收层包括孔，光穿过该孔不改变到玻璃基底层。

公开(公告)号：US06803267B1

公开(公告)日：2004-10-12

申请号：US10614484

申请日：2003-07-07

申请人： Ramkumar Subramanian ,  Christopher F. Lyons ,  Matthew S. Buynoski ,  Patrick K. Cheung ,  Angela T. Hui ,  Ashok M. Khathuria ,  Sergey D. Lopatin ,  Minh Van Ngo ,  Jane V. Oglesby ,  Terence C. Tong ,  James J. Xie

发明人： Ramkumar Subramanian ,  Christopher F. Lyons ,  Matthew S. Buynoski ,  Patrick K. Cheung ,  Angela T. Hui ,  Ashok M. Khathuria ,  Sergey D. Lopatin ,  Minh Van Ngo ,  Jane V. Oglesby ,  Terence C. Tong ,  James J. Xie

IPC分类号： H01L21336

CPC分类号： H01L27/28 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  H01L51/0018

摘要： The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, and operatively coupling the an upper electrode to the lower electrode through the organic semiconductor material and the passive material. Patterning of the organic semiconductor material is achieved by depositing a silicon-based resist over the organic semiconductor, irradiating portions of the silicon-based resist and patterning the silicon-based resist to remove the irradiated portions of the silicon-based resist. Thereafter, the exposed organic semiconductor can be patterned, and the non-irradiated silicon-based resist can be stripped to expose the organic semiconductor material that can be employed as a memory cell for single and multi-cell memory devices. A partitioning component can be integrated with the memory device to facilitate stacking memory devices and programming, reading, writing and erasing memory elements.

摘要翻译： 本发明提供一种制造有机存储器件的方法，其中所述制造方法包括形成下电极，在所述下电极的表面上沉积无源材料，在所述被动材料上施加有机半导体材料，以及将所述有源半导体材料 上电极通过有机半导体材料和被动材料到下电极。 有机半导体材料的图案化是通过在有机半导体上沉积硅基抗蚀剂，照射硅基抗蚀剂的部分并图案化硅基抗蚀剂以除去硅基抗蚀剂的照射部分来实现的。 此后，可以对暴露的有机半导体进行构图，并且可以剥离未照射的硅基抗蚀剂以暴露可用作单电池和多电池存储器件的存储器单元的有机半导体材料。 分区组件可以与存储器件集成，以便于堆叠存储器件和编程，读取，写入和擦除存储器元件。

公开(公告)号：US06790790B1

公开(公告)日：2004-09-14

申请号：US10302227

申请日：2002-11-22

申请人： Christopher F. Lyons ,  Bharath Rangarajan

发明人： Christopher F. Lyons ,  Bharath Rangarajan

IPC分类号： H01L2131

CPC分类号： H01L21/31058 ,  H01L21/02118 ,  H01L21/0212

摘要： Disclosed are methods for processing a low k material involving providing a low k material layer comprising one or more low k polymer materials and one or more high modulus fillers on a semiconductor substrate, and chemical mechanical polishing the low k material layer so as to remove a portion of the low k material layer from the semiconductor substrate without substantially damaging unremoved portions of the low k material layer. In this connection, low k material layers for a semiconductor structure containing one or more low k polymer materials and one or more high modulus fillers are disclosed, as well as methods of making the low k material layers.

摘要翻译： 公开了一种处理低k材料的方法，包括在半导体衬底上提供包含一种或多种低k聚合物材料和一种或多种高模量填料的低k材料层，以及化学机械抛光低k材料层，以除去 来自半导体衬底的低k材料层的一部分，而不会基本上损坏低k材料层的未被除去的部分。 在这方面，公开了用于包含一种或多种低k聚合物材料和一种或多种高模量填料的半导体结构的低k材料层，以及制备低k材料层的方法。