公开(公告)号：US10726010B2

公开(公告)日：2020-07-28

申请号：US13603302

申请日：2012-09-04

申请人： Rafi Ahmed ,  Chun-Chieh Lin ,  Mohamed Zait

发明人： Rafi Ahmed ,  Chun-Chieh Lin ,  Mohamed Zait

IPC分类号： G06F16/2453

摘要： A method, apparatus, and stored instructions are provided for transforming a query representation by unnesting a predicate condition that is based on whether or not a result exists for a subquery of the predicate condition. An initial query representation is received. The initial query representation represents an initial query that includes an EXISTS-equivalent predicate or a NOT-EXISTS-equivalent predicate and at least one other predicate in a disjunction. The initial query representation is transformed into a semantically equivalent transformed query representation that represents a transformed query. The transformed query includes, instead of the EXISTS-equivalent predicate or a NOT-EXISTS-equivalent predicate, a join operator that references the data object. The transformed query representation, when used for execution, causes the at least one other predicate to be applied separately from a join operation caused by the join operator such that execution of the initial representation is semantically equivalent to execution of the transformed representation.

公开(公告)号：US07659587B2

公开(公告)日：2010-02-09

申请号：US11746141

申请日：2007-05-09

申请人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

发明人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

IPC分类号： H01L21/00

CPC分类号： H01L21/28167 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/7846

摘要： A CMOS integrated circuit includes a substrate having an NMOS region with a P-well and a PMOS region with an N-well. A shallow trench isolation (STI) region is formed between the NMOS and PMOS regions and a composite silicon layer comprising a strained SiGe layer is formed over said P well region and over said N well region. The composite silicon layer is disconnected at the STI region. Gate electrodes are then formed on the composite layer in the NMOS and PMOS regions.

摘要翻译： CMOS集成电路包括具有带有P阱的NMOS区域和具有N阱的PMOS区域的衬底。 在NMOS和PMOS区之间形成浅沟槽隔离（STI）区，并且在所述P阱区和所述N阱区之上形成包含应变SiGe层的复合硅层。 复合硅层在STI区域断开。 然后在NMOS和PMOS区域中的复合层上形成栅电极。

公开(公告)号：US07293340B1

公开(公告)日：2007-11-13

申请号：US11724271

申请日：2007-03-15

申请人： Hsiang-Yuan Tsao ,  Chun-Chieh Lin

发明人： Hsiang-Yuan Tsao ,  Chun-Chieh Lin

IPC分类号： B23P15/00 ,  B23C1/12

CPC分类号： B23Q1/5406 ,  B23Q2210/004 ,  B23Q2220/006 ,  Y10T29/49826 ,  Y10T29/49904 ,  Y10T409/307672 ,  Y10T409/308512

摘要： This invention discloses a direct drive spindle assembly including a main fork formed by a base and a parallel pair of spaced fork arms and rotated about a first rotational axis. Moreover, the direct drive spindle assembly includes a first drive established by a hollow housing, a first motor stator and a first motor rotor, wherein the first motor rotor coupled with the base of the main fork drives the main fork to rotate about the first rotational axis. Furthermore, the direct drive spindle assembly includes a second drive contained in a room between the fork arms of the main fork and established by a second motor stator concentric with a second rotational axis, a second motor rotor and a rotor transmission ring, wherein the second rotational axis is perpendicular to the first rotational axis and the second motor stator is coupled with the fork arms of the main fork. In addition, the direct drive spindle assembly includes a spindle box having an orthogonal cross structure. A first arm of the rotor transmission ring is coupled with the second motor rotor and a second arm of the structure is connected to a spindle head. The feature of the present invention is that after the second drive is fit in the room between the above-mentioned paired fork arms of the main fork and then combined with the base of the main fork and firmly locked in the right position, the whole structure can achieve preferred precision.

摘要翻译： 本发明公开了一种直接驱动主轴组件，其包括由基座形成的主叉和平行的一对间隔的叉臂，并绕第一旋转轴线旋转。 此外，直接驱动主轴组件包括由中空壳体建立的第一驱动器，第一电动机定子和第一电动机转子，其中与主叉的基座联接的第一电动机转子驱动主叉绕第一旋转 轴。 此外，直接驱动主轴组件包括容纳在主叉的叉臂之间的房间中并由与第二旋转轴同心的第二电动机定子建立的第二驱动器，第二电动机转子和转子传动环，其中第二驱动主轴 旋转轴线垂直于第一旋转轴线，而第二电动机定子与主叉的叉臂连接。 此外，直接驱动主轴组件包括具有正交交叉结构的主轴箱。 转子传动环的第一臂与第二电动机转子耦合，并且该结构的第二臂连接到主轴头。 本发明的特征在于，在将第二驱动装配在主叉的上述成对叉臂之间的房间中，然后与主叉的基部结合并牢固地锁定在正确的位置时，整个结构 可以实现优先的精度。

公开(公告)号：US20070164369A1

公开(公告)日：2007-07-19

申请号：US11714416

申请日：2007-03-06

申请人： Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

发明人： Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

IPC分类号： H01L29/76

CPC分类号： H01L29/1054 ,  H01L21/02142 ,  H01L21/265 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7834

摘要： A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

摘要翻译： 一种方法包括在半导体衬底上提供半导体合金层，在半导体合金层上形成栅极结构，在半导体衬底的栅极结构的两侧形成源区和漏极区，去除半导体合金层的至少一部分 覆盖源极和漏极区域，并且在源极和漏极区域上形成金属硅化物区域。

公开(公告)号：US07226832B2

公开(公告)日：2007-06-05

申请号：US11227264

申请日：2005-09-15

申请人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

发明人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

IPC分类号： H01L21/8238

CPC分类号： H01L21/28167 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/7846

摘要： A CMOS integrated circuit includes a substrate having an NMOS region with a P-well and a PMOS region with an N-well. A shallow trench isolation (STI) region is formed between the NMOS and PMOS regions and a composite silicon layer comprising a strained SiGe layer is formed over said P well region and over said N well region. The composite silicon layer is disconnected at the STI region. Gate electrodes are then formed on the composite layer in the NMOS and PMOS regions.

摘要翻译： CMOS集成电路包括具有带有P阱的NMOS区域和具有N阱的PMOS区域的衬底。 在NMOS和PMOS区之间形成浅沟槽隔离（STI）区，并且在所述P阱区和所述N阱区之上形成包含应变SiGe层的复合硅层。 复合硅层在STI区域断开。 然后在NMOS和PMOS区域中的复合层上形成栅电极。

公开(公告)号：US20060091551A1

公开(公告)日：2006-05-04

申请号：US10977596

申请日：2004-10-29

申请人： Chun-Chieh Lin ,  Shih-Wei Chou ,  Minghsing Tsai

发明人： Chun-Chieh Lin ,  Shih-Wei Chou ,  Minghsing Tsai

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76816 ,  C25D3/58 ,  C25D5/022 ,  C25D5/10 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76877

摘要： A method of forming a copper filled semiconductor feature having improved bulk properties including providing a semiconductor process wafer having a process surface including an opening for forming a semiconductor feature; depositing at least one metal dopant containing layer over the opening to form a thermally diffusive relationship to a subsequently deposited copper layer; depositing said copper layer to substantially fill the opening; and, thermally treating the semiconductor process wafer for a time period sufficient to distribute at least a portion of the metal dopants to collect along at least a portion of the periphery of said copper layer including a portion of said copper layer grain boundaries.

摘要翻译： 一种形成具有改善的体积特性的铜填充半导体特征的方法，包括提供具有包括用于形成半导体特征的开口的工艺表面的半导体工艺晶片; 在所述开口上沉积至少一种含金属掺杂剂层以形成与随后沉积的铜层的热扩散关系; 沉积所述铜层以基本上填充所述开口; 以及对所述半导体工艺晶片进行热处理足以使所述金属掺杂剂的至少一部分分布在包含所述铜层晶界的一部分的所述铜层的周边的至少一部分的时间段内收集。

公开(公告)号：US20060081952A1

公开(公告)日：2006-04-20

申请号：US11163118

申请日：2005-10-05

申请人： Chun-Chieh Lin

发明人： Chun-Chieh Lin

IPC分类号： H01L43/00

CPC分类号： H01L27/228 ,  H01L43/08

摘要： Disclosed herein is a magnetoresistive structure having a non-planar form. Embodiments of the present MR structure includes those having at least one inflection between a first portion of the MR structure that is somewhat vertical relative to a substrate and a second portion of the MR structure that is somewhat horizontal relative to the substrate. Such a structure can be used for memory device, for example an MRAM memory device, wherein the memory density is increased compared to devices having prior planar MR structures without reducing the surface area of the MR structures.

摘要翻译： 本文公开了具有非平面形式的磁阻结构。 本发明的MR结构的实施例包括那些在MR结构的第一部分之间相对于衬底稍微垂直的第一部分和MR结构相对于衬底稍微水平的第二部分的至少一个拐点。 这种结构可以用于存储器件，例如MRAM存储器件，其中与具有先前的平面MR结构的器件相比，存储器密度增加而不减小MR结构的表面积。

公开(公告)号：US06875655B2

公开(公告)日：2005-04-05

申请号：US10802564

申请日：2004-03-17

申请人： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Hui Lin ,  Fu-Liang Yang ,  Chia-Shiung Tsai ,  Chanming Hu

发明人： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Hui Lin ,  Fu-Liang Yang ,  Chia-Shiung Tsai ,  Chanming Hu

IPC分类号： H01L21/02 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/0207 ,  H01L27/10817 ,  H01L28/91

摘要： A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

摘要翻译： 实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。 该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。 在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。 然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案以在电容器之间提供保护性层间电介质结构。 保护结构可防止在后续处理期间损坏底部电极。 蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。 在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

公开(公告)号：US06656844B1

公开(公告)日：2003-12-02

申请号：US09981437

申请日：2001-10-18

申请人： Chun-Chieh Lin ,  Wong-Cheng Shih

发明人： Chun-Chieh Lin ,  Wong-Cheng Shih

IPC分类号： H01L21301

CPC分类号： H01L21/32136 ,  H01L21/31116 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91

摘要： A method of forming a DRAM capacitor structure featuring increased surface area, has been developed. The method features a polysilicon top plate structure located overlying an array comprised of individual polysilicon storage node structures. Each polysilicon storage node structure is comprised with tall, vertical features, and additional surface area is obtained via removal of butted insulator layer from a first group of surfaces of the storage node structures. Insulator layer remains butted to a second group of storage node structure surfaces to prevent collapse of the tall, vertical features of the storage node structures during subsequent processing sequences.

摘要翻译： 已经开发了形成具有增加的表面积的DRAM电容器结构的方法。 该方法具有位于由单个多晶硅存储节点结构组成的阵列上方的多晶硅顶板结构。 每个多晶硅存储节点结构包括高垂直特征，并且通过从存储节点结构的第一组表面去除对接的绝缘体层来获得额外的表面积。 绝缘体层保持对接到第二组存储节点结构表面，以防止后续处理序列期间存储节点结构的高垂直特征的崩溃。