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    DRAM capacitor structure with increased electrode support for preventing process damage and exposed electrode surface for increasing capacitor area
    1.
    发明授权
    DRAM capacitor structure with increased electrode support for preventing process damage and exposed electrode surface for increasing capacitor area 有权
    DRAM电容器结构具有增加的电极支持，用于防止工艺损坏和暴露的电极表面，以增加电容器面积

    公开(公告)号：US07161204B2

    公开(公告)日：2007-01-09

    申请号：US11098112

    申请日：2005-04-04

    申请人： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Shiung Tsai ,  Fu-Liang Yang ,  Chia-Hui Lin ,  Chanming Hu

    发明人： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Shiung Tsai ,  Fu-Liang Yang ,  Chia-Hui Lin ,  Chanming Hu

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/10852 ,  H01L27/0207 ,  H01L27/10817 ,  H01L28/91

    摘要： A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

    摘要翻译： 实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。 该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。 在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。 然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案化，以在电容器之间提供保护层间电介质结构。 保护结构可防止在后续处理期间损坏底部电极。 蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。 在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

    Method of forming DRAM capactiors with protected outside crown surface for more robust structures
    2.
    发明申请
    Method of forming DRAM capactiors with protected outside crown surface for more robust structures 有权
    用于形成具有受保护的外表冠表面的DRAM盖板的方法用于更坚固的结构

    公开(公告)号：US20050179076A1

    公开(公告)日：2005-08-18

    申请号：US11098112

    申请日：2005-04-04

    申请人： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Hui Lin ,  Fu-Liang Yang ,  Chia-Shiung Tsai ,  Chanming Hu

    发明人： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Hui Lin ,  Fu-Liang Yang ,  Chia-Shiung Tsai ,  Chanming Hu

    IPC分类号： H01L21/02 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L27/0207 ,  H01L27/10817 ,  H01L28/91

    摘要： A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

    摘要翻译： 实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。 该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。 在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。 然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案以在电容器之间提供保护性层间电介质结构。 保护结构可防止在后续处理期间损坏底部电极。 蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。 在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

    Method of forming DRAM capacitors with protected outside crown surface for more robust structures
    3.
    发明授权
    Method of forming DRAM capacitors with protected outside crown surface for more robust structures 有权
    形成具有受保护的外冠表面的DRAM电容器的方法用于更坚固的结构

    公开(公告)号：US06875655B2

    公开(公告)日：2005-04-05

    申请号：US10802564

    申请日：2004-03-17

    申请人： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Hui Lin ,  Fu-Liang Yang ,  Chia-Shiung Tsai ,  Chanming Hu

    发明人： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Hui Lin ,  Fu-Liang Yang ,  Chia-Shiung Tsai ,  Chanming Hu

    IPC分类号： H01L21/02 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L27/0207 ,  H01L27/10817 ,  H01L28/91

    摘要： A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

    摘要翻译： 实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。 该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。 在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。 然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案以在电容器之间提供保护性层间电介质结构。 保护结构可防止在后续处理期间损坏底部电极。 蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。 在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

    MEMS structures and methods for forming the same
    4.
    发明授权
    MEMS structures and methods for forming the same 有权
    MEMS结构及其形成方法

    公开(公告)号：US08836055B2

    公开(公告)日：2014-09-16

    申请号：US13250078

    申请日：2011-09-30

    申请人： Lung Yuan Pan ,  Lan-Lin Chao ,  Chia-Shiung Tsai

    发明人： Lung Yuan Pan ,  Lan-Lin Chao ,  Chia-Shiung Tsai

    IPC分类号： H01L31/115

    CPC分类号： H01G5/18 ,  B81B3/001 ,  B81B2201/0221 ,  H01L28/60

    摘要： A device includes a micro-electro-mechanical system (MEMS) device, which includes a movable element and a fixed element. The movable element and the fixed element form two capacitor plates of a capacitor, with an air-gap between the movable element and the fixed element acting as a capacitor insulator of the capacitor. At least one of the movable element and the fixed element has a rugged surface.

    摘要翻译： 一种装置包括微电子机械系统（MEMS）装置，其包括可移动元件和固定元件。 可移动元件和固定元件形成电容器的两个电容器板，可动元件和固定元件之间的气隙用作电容器的电容器绝缘体。 可移动元件和固定元件中的至少一个具有粗糙的表面。

    Methods of bonding caps for MEMS devices
    5.
    发明授权
    Methods of bonding caps for MEMS devices 有权
    MEMS器件封装方法

    公开(公告)号：US08790946B2

    公开(公告)日：2014-07-29

    申请号：US13365043

    申请日：2012-02-02

    申请人： Xin-Hua Huang ,  Ping-Yin Liu ,  Li-Cheng Chu ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chun-Wen Cheng ,  Chia-Shiung Tsai

    发明人： Xin-Hua Huang ,  Ping-Yin Liu ,  Li-Cheng Chu ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chun-Wen Cheng ,  Chia-Shiung Tsai

    IPC分类号： H01L21/52

    CPC分类号： B23K20/002 ,  B23K20/023

    摘要： A method includes bonding a first bond layer to a second bond layer through eutectic bonding. The step of bonding includes heating the first bond layer and the second bond layer to a temperature higher than a eutectic temperature of the first bond layer and the second bond layer, and performing a pumping cycle. The pumping cycle includes applying a first force to press the first bond layer and the second bond layer against each other. After the step of applying the first force, a second force lower than the first force is applied to press the first bond layer and the second bond layer against each other. After the step of applying the second force, a third force higher than the second force is applied to press the first bond layer and the second bond layer against each other.

    摘要翻译： 一种方法包括通过共晶接合将第一接合层结合到第二接合层。 接合步骤包括将第一接合层和第二接合层加热至高于第一接合层和第二接合层的共晶温度的温度，并进行泵送循环。 泵送循环包括施加第一力以将第一接合层和第二接合层相互挤压。 在施加第一力的步骤之后，施加比第一力小的第二力以将第一接合层和第二接合层相互挤压。 在施加第二力的步骤之后，施加比第二力高的第三力以将第一接合层和第二接合层相互挤压。

    Semiconductor having a high aspect ratio via
    8.
    发明授权
    Semiconductor having a high aspect ratio via 有权
    具有高纵横比的半导体

    公开(公告)号：US08207595B2

    公开(公告)日：2012-06-26

    申请号：US12898408

    申请日：2010-10-05

    申请人： Yuan-Chih Hsieh ,  Richard Chu ,  Ming-Tung Wu ,  Martin Liu ,  Lan-Lin Chao ,  Chia-Shiung Tsai

    发明人： Yuan-Chih Hsieh ,  Richard Chu ,  Ming-Tung Wu ,  Martin Liu ,  Lan-Lin Chao ,  Chia-Shiung Tsai

    IPC分类号： H01L29/40

    CPC分类号： H01L23/5384 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a substrate wafer, a dielectric layer overlying the substrate wafer, a patterned conductor layer in the dielectric layer, and a first barrier layer overlying the conductor layer. A silicon top wafer is bonded to the dielectric layer. A via is formed through the top wafer and a portion of the dielectric layer to the first barrier layer. A sidewall dielectric layer is formed along inner walls of the via, adjacent the top wafer to a distance below an upper surface of the top wafer, forming a sidewall dielectric layer shoulder. A sidewall barrier layer is formed inward of the sidewall dielectric layer, lining the via from the first barrier layer to the upper surface of the top wafer. A conductive layer fills the via and a top barrier layer is formed on the conductive layer, the sidewall barrier layer, and the top wafer.

    摘要翻译： 半导体器件包括衬底晶片，覆盖衬底晶片的电介质层，电介质层中的图案化导体层和覆盖导体层的第一势垒层。 硅顶片结合到电介质层。 通孔通过顶部晶片和介电层的一部分形成到第一阻挡层。 侧壁电介质层沿通孔的内壁形成，与顶部晶片相邻，距离顶部晶片的上表面一定距离，形成侧壁电介质层的肩部。 在侧壁电介质层的内侧形成侧壁阻挡层，将通孔从第一阻挡层衬套到顶部晶片的上表面。 导电层填充通孔，并且在导电层，侧壁阻挡层和顶部晶片上形成顶部阻挡层。

    Magnetic memory cells and manufacturing methods
    10.
    发明申请
    Magnetic memory cells and manufacturing methods 有权
    磁记忆体和制造方法

    公开(公告)号：US20070096230A1

    公开(公告)日：2007-05-03

    申请号：US11610760

    申请日：2006-12-14

    申请人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

    发明人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

    IPC分类号： H01L43/00 ,  H01L29/82

    CPC分类号： H01L43/12 ,  H01L27/228

    摘要： An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.

    摘要翻译： 改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。 通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层，然后使用平坦化处理去除绝缘层的部分的方法，通过形成改进的磁阻存储器件来简化缩短的距离。 然后可以在掩模层中形成导电通孔，例如使用镶嵌工艺。 然后可以在掩模层和导电通孔上形成导电存储器线。