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    Differentially metal doped copper damascenes
    1.
    发明申请
    Differentially metal doped copper damascenes 审中-公开
    差异化金属掺杂铜大马士革

    公开(公告)号：US20060091551A1

    公开(公告)日：2006-05-04

    申请号：US10977596

    申请日：2004-10-29

    申请人： Chun-Chieh Lin ,  Shih-Wei Chou ,  Minghsing Tsai

    发明人： Chun-Chieh Lin ,  Shih-Wei Chou ,  Minghsing Tsai

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L21/76816 ,  C25D3/58 ,  C25D5/022 ,  C25D5/10 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76877

    摘要： A method of forming a copper filled semiconductor feature having improved bulk properties including providing a semiconductor process wafer having a process surface including an opening for forming a semiconductor feature; depositing at least one metal dopant containing layer over the opening to form a thermally diffusive relationship to a subsequently deposited copper layer; depositing said copper layer to substantially fill the opening; and, thermally treating the semiconductor process wafer for a time period sufficient to distribute at least a portion of the metal dopants to collect along at least a portion of the periphery of said copper layer including a portion of said copper layer grain boundaries.

    摘要翻译： 一种形成具有改善的体积特性的铜填充半导体特征的方法，包括提供具有包括用于形成半导体特征的开口的工艺表面的半导体工艺晶片; 在所述开口上沉积至少一种含金属掺杂剂层以形成与随后沉积的铜层的热扩散关系; 沉积所述铜层以基本上填充所述开口; 以及对所述半导体工艺晶片进行热处理足以使所述金属掺杂剂的至少一部分分布在包含所述铜层晶界的一部分的所述铜层的周边的至少一部分的时间段内收集。

    Method to remove copper without pattern density effect
    3.
    发明授权
    Method to remove copper without pattern density effect 失效
    去除铜的方法，无图案密度效应

    公开(公告)号：US06995089B2

    公开(公告)日：2006-02-07

    申请号：US10434741

    申请日：2003-05-08

    申请人： Shih-Wei Chou ,  Minghsing Tsai ,  Winston Shue

    发明人： Shih-Wei Chou ,  Minghsing Tsai ,  Winston Shue

    IPC分类号： H01L21/302

    CPC分类号： H01L21/32115 ,  B23H5/08 ,  C23F1/18 ,  C25F3/02 ,  H01L21/32134 ,  H01L21/7684 ,  H05K3/06 ,  H05K3/07 ,  H05K3/107 ,  H05K2203/0353 ,  H05K2203/1476

    摘要： A new method is provided that allows for the application of electropolish for removal of copper and that is independent of pattern density of the removed copper. Electropolish of the copper is first accomplished by reversing current in the H2SO4 or H3PO4 solution. After identifying the endpoint of the electropolish, chemical etching of the copper in a H2SO4 or H3PO4 solution is continued, in this manner avoiding effects of high current density introduced by pattern density.

    摘要翻译： 提供了一种新的方法，其允许使用电解抛光以除去铜，并且不依赖于去除的铜的图案密度。 铜的电解抛光首先通过在H 2 SO 3 / SO 3 H 4 SO 3 / SO 3 H 4 O 3 / 。 在鉴定了电解抛光物质的终点之后，在H 2 SO 3或4 H 3 PO 4中的铜的化学蚀刻， 继续以这种方式避免由图案密度引入的高电流密度的影响。

    Silicide structure for ultra-shallow junction for MOS devices
    4.
    发明授权
    Silicide structure for ultra-shallow junction for MOS devices 有权
    用于MOS器件的超浅结的硅化物结构

    公开(公告)号：US07332435B2

    公开(公告)日：2008-02-19

    申请号：US11072038

    申请日：2005-03-04

    申请人： Chien-Hsueh Shih ,  Shih-Wei Chou ,  Hung-Wen Su ,  Minghsing Tsai

    发明人： Chien-Hsueh Shih ,  Shih-Wei Chou ,  Hung-Wen Su ,  Minghsing Tsai

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28518 ,  H01L29/66507 ,  H01L29/66515 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of forming a semiconductor device comprising: forming a gate dielectric layer over a channel region; forming a gate electrode on the gate dielectric layer; forming source/drain regions substantially aligned with respective edges of the gate electrode with the channel region therebetween; forming a thin metal layer on the source/drain regions; forming a metal alloy layer on the thin metal layer; and transforming the thin metal layer into a low resistance metal silicide.

    摘要翻译： 一种形成半导体器件的方法，包括：在沟道区上形成栅介电层; 在所述栅极电介质层上形成栅电极; 形成与所述栅电极的各个边缘基本对准的源极/漏极区域，其间具有沟道区域; 在源/漏区上形成薄金属层; 在所述薄金属层上形成金属合金层; 并将薄金属层转变成低电阻金属硅化物。

    Novel silicide structure for ultra-shallow junction for MOS devices
    5.
    发明申请
    Novel silicide structure for ultra-shallow junction for MOS devices 有权
    用于MOS器件的超浅结的新型硅化物结构

    公开(公告)号：US20060205214A1

    公开(公告)日：2006-09-14

    申请号：US11072038

    申请日：2005-03-04

    申请人： Chien-Hsueh Shih ,  Shih-Wei Chou ,  Hung-Wen Su ,  Minghsing Tsai

    发明人： Chien-Hsueh Shih ,  Shih-Wei Chou ,  Hung-Wen Su ,  Minghsing Tsai

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28518 ,  H01L29/66507 ,  H01L29/66515 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of forming a semiconductor device comprising: forming a gate dielectric layer over a channel region; forming a gate electrode on the gate dielectric layer; forming source/drain regions substantially aligned with respective edges of the gate electrode with the channel region therebetween; forming a thin metal layer on the source/drain regions; forming a metal alloy layer on the thin metal layer; and transforming the thin metal layer into a low resistance metal silicide.

    摘要翻译： 一种形成半导体器件的方法，包括：在沟道区上形成栅介电层; 在所述栅极电介质层上形成栅电极; 形成与所述栅电极的各个边缘基本对准的源极/漏极区域，其间具有沟道区域; 在源/漏区上形成薄金属层; 在所述薄金属层上形成金属合金层; 并将薄金属层转变成低电阻金属硅化物。

    GAP FILLING METHOD FOR DUAL DAMASCENE PROCESS
    6.
    发明申请
    GAP FILLING METHOD FOR DUAL DAMASCENE PROCESS 有权
    GAP填充方法双重DAMASCENE过程

    公开(公告)号：US20120319278A1

    公开(公告)日：2012-12-20

    申请号：US13161701

    申请日：2011-06-16

    申请人： Chun-Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai ,  Syun-Ming Jang

    发明人： Chun-Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai ,  Syun-Ming Jang

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L21/76877 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/511 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.

    摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括形成具有多个第一开口的图案化电介质层。 该方法包括在图案化的介电层上形成导电衬垫层，导电衬垫层部分填充第一开口。 该方法包括在第一开口之外的导电衬垫层的部分上形成沟槽掩模层，从而形成多个第二开口，其中一部分形成在第一开口上。 该方法包括在第一开口中沉积导电材料以形成多个通孔，并且在第二开口中形成多个金属线。 该方法包括去除沟槽掩模层。