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145 条记录 (耗时 0.033 秒)

    Method and apparatus for compensating for bitline leakage current
    81.
    发明授权
    Method and apparatus for compensating for bitline leakage current 有权
    用于补偿位线泄漏电流的方法和装置

    公开(公告)号：US07161844B2

    公开(公告)日：2007-01-09

    申请号：US10814443

    申请日：2004-03-30

    申请人： Vishal Sarin ,  Hieu Van Tran ,  Dana Lee

    发明人： Vishal Sarin ,  Hieu Van Tran ,  Dana Lee

    IPC分类号： G11C7/10

    CPC分类号： G11C16/0433 ,  G11C7/12 ,  G11C16/10

    摘要： A bitline leakage current compensation circuit for compensating for leakage current in an operational memory array by measuring the leakage current in a non-operational memory array or a dummy memory array and providing a feedback signal to a current source or providing the compensation current.

    摘要翻译： 一种位线泄漏电流补偿电路，用于通过测量非操作存储器阵列或虚拟存储器阵列中的漏电流并向电流源提供反馈信号或提供补偿电流来补偿操作存储器阵列中的漏电流。

    BIDIRECTIONAL SPLIT GATE NAND FLASH MEMORY STRUCTURE AND ARRAY, METHOD OF PROGRAMMING, ERASING AND READING THEREOF, AND METHOD OF MANUFACTURING
    82.
    发明申请
    BIDIRECTIONAL SPLIT GATE NAND FLASH MEMORY STRUCTURE AND ARRAY, METHOD OF PROGRAMMING, ERASING AND READING THEREOF, AND METHOD OF MANUFACTURING 有权
    双向分割门NAND闪存存储器结构和阵列，编程，擦除和读取方法及其制造方法

    公开(公告)号：US20060273378A1

    公开(公告)日：2006-12-07

    申请号：US11134557

    申请日：2005-05-20

    申请人： Feng Gao ,  Ya-Fen Lin ,  John Cooksey ,  Changyuan Chen ,  Yuniarto Widjaja ,  Dana Lee

    发明人： Feng Gao ,  Ya-Fen Lin ,  John Cooksey ,  Changyuan Chen ,  Yuniarto Widjaja ,  Dana Lee

    IPC分类号： H01L29/792

    CPC分类号： H01L29/42336 ,  G11C16/0425 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42328

    摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.

    摘要翻译： 在第一导电类型的半导体衬底上形成分离栅极NAND闪速存储器结构。 NAND结构包括第二导电类型的第一区域和第二导电类型的第二区域，与第一区域间隔开，由此在其间限定沟道区域。 多个浮动栅极彼此间隔开并且各自与沟道区域绝缘。 多个控制栅极彼此间隔开，每个控制栅极与沟道区域绝缘。 每个控制栅极位于一对浮动栅极之间，并且电容耦合到该对浮置栅极。 多个选择栅极彼此间隔开，每个选择栅极与沟道区域绝缘。 每个选择门位于一对浮动门之间。

    Multi-bit ROM cell, for storing one of n>4 possible states and having bi-directional read, an array of such cells, and a method for making the array
    84.
    发明授权
    Multi-bit ROM cell, for storing one of n>4 possible states and having bi-directional read, an array of such cells, and a method for making the array 有权
    用于存储n> 4个可能状态之一并且具有双向读取的多位ROM单元，这种单元的阵列，以及用于制作阵列的方法

    公开(公告)号：US06992909B2

    公开(公告)日：2006-01-31

    申请号：US11157318

    申请日：2005-06-20

    申请人： Bomy Chen ,  Kai Man Yue ,  Dana Lee ,  Feng Gao

    发明人： Bomy Chen ,  Kai Man Yue ,  Dana Lee ,  Feng Gao

    IPC分类号： G11C17/00

    CPC分类号： H01L27/112 ,  G11C11/5692 ,  G11C17/12 ,  H01L27/1126 ,  H01L27/11266

    摘要： A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together. ROM cells in the same column have the first regions connected in a common first column, and second regions connected in common second column. Finally, ROM cells in adjacent columns to one side share a common first column, and cells in adjacent columns to another side share a common second column.

    摘要翻译： 多位只读存储器（ROM）单元的阵列位于具有第一浓度的第一导电类型的半导体衬底中。 每个ROM单元具有在基板中彼此间隔开的第二导电类型的第一和第二区域。 通道在第一和第二区域之间。 通道具有三个部分，第一部分，第二部分和第三部分。 门间隔开并与通道的至少第二部分绝缘。 每个ROM单元具有多个N个可能状态中的一个，其中N大于2.每个ROM单元的状态由存在或不存在在通道的第一部分中形成并与通道的第一部分相邻 第一区域和/或与第二区域相邻的通道的第三部分。 在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。 ROM单元的阵列被布置成多个行和列，其中同一行中的ROM单元的门连接在一起。 同一列中的ROM单元具有连接在公共第一列中的第一区域和连接在公共第二列中的第二区域。 最后，一侧的相邻列中的ROM单元共享一个共同的第一列，另一侧的相邻列中的单元格共享第二列。

    Integrated semiconductor metal-insulator-semiconductor capacitor
    85.
    发明申请
    Integrated semiconductor metal-insulator-semiconductor capacitor 审中-公开
    集成半导体金属绝缘体 - 半导体电容器

    公开(公告)号：US20060017084A1

    公开(公告)日：2006-01-26

    申请号：US10897045

    申请日：2004-07-22

    申请人： Feng Gao ,  Changyuan Chen ,  Vishal Sarin ,  William Saiki ,  Hieu Tran ,  Dana Lee

    发明人： Feng Gao ,  Changyuan Chen ,  Vishal Sarin ,  William Saiki ,  Hieu Tran ,  Dana Lee

    IPC分类号： H01L29/76

    CPC分类号： H01L27/0805 ,  H01L27/0811 ,  H01L29/94

    摘要： An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration. A capacitor which has high capacitance densities, low process complexity, ambipolar operation, low voltage and temperature coefficient, low external parasitic resistance and capacitance and good matching characteristics for use in analog designs that can be integrated with existing semiconductor processes results.

    摘要翻译： 集成的MIS电容器具有两个基本相同的MIS电容器。 第一电容器包括在半导体衬底中与第一导电类型的沟道区相邻的第一导电类型的第一区域。 半导体衬底具有第二导电类型。 栅电极与第一电容器的沟道区隔离并隔开。 第二电容器基本上与第一电容器相同，并且形成在相同的半导体衬底中。 第一电容器的栅电极电连接到第二电容器的第一区域，并且第二电容器的栅极电连接到第一电容器的第一区域。 以这种方式，电容器以反并联配置连接。 具有高电容密度，低工艺复杂性，双极性操作，低电压和温度系数，低外部寄生电阻和电容以及用于可与现有半导体工艺结合的模拟设计的良好匹配特性的电容器。

    Vertical NROM and methods for making thereof
    86.
    发明授权
    Vertical NROM and methods for making thereof 有权
    垂直NROM及其制造方法

    公开(公告)号：US06940125B2

    公开(公告)日：2005-09-06

    申请号：US10407627

    申请日：2003-04-04

    申请人： Sohrab Kianian ,  Dana Lee

    发明人： Sohrab Kianian ,  Dana Lee

    IPC分类号： H01L21/8246 ,  H01L27/115 ,  H01L29/792 ,  H01L29/76

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  H01L29/7926

    摘要： Vertical NROM devices are made in a substantially single crystalline silicon substrate having a planar surface. The vertical NROM cell and device has a first region and a second region spaced apart from one another by a channel. A dielectric is spaced apart from the channel to capture charges injected from the channel onto the dielectric. A gate is positioned over the dielectric and spaced apart therefrom and controls the flow of current through the channel. In the improvement of the present invention, a portion of the channel is substantially perpendicular to the top planar surface of the substrate. Methods for making the vertical NROM cell and array are also disclosed.

    摘要翻译： 垂直NROM器件制成具有平坦表面的基本单晶硅衬底。 垂直NROM单元和器件具有通过通道彼此间隔开的第一区域和第二区域。 电介质与通道间隔开以捕获从通道注入到电介质上的电荷。 栅极位于电介质上并与其间隔开并控制通过通道的电流。 在本发明的改进中，通道的一部分基本上垂直于基板的顶部平坦表面。 还公开了制造垂直NROM单元和阵列的方法。

    Array of integrated circuit units with strapping lines to prevent punch through
    88.
    发明授权
    Array of integrated circuit units with strapping lines to prevent punch through 有权
    具有捆扎线的集成电路单元阵列，以防止穿透

    公开(公告)号：US06822287B1

    公开(公告)日：2004-11-23

    申请号：US10452027

    申请日：2003-05-30

    申请人： Dana Lee ,  Yaw Wen Hu

    发明人： Dana Lee ,  Yaw Wen Hu

    IPC分类号： H01L29788

    CPC分类号： H01L29/66825 ,  G11C5/063 ,  G11C16/0425 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/42336 ,  H01L29/7885

    摘要： An array of non-volatile memory cells is arranged in a plurality of rows and columns where each cell has a first region and a second region spaced apart from one another with a channel region therebetween for the conduction of charges between the first region and the second region. A first plurality of row lines electrically connect the second region of cells in the same row. A plurality of column lines electrically connect the first region of cells in the same column. A plurality of strap lines connect certain of the row lines with each strap line electrically connecting a second plurality of row lines not immediately adjacent to one another, wherein row lines connected to a first strap line are interleaved with row lines connected to a second strap line.

    摘要翻译： 非易失性存储单元的阵列被布置在多个行和列中，其中每个单元具有第一区域和彼此间隔开的第二区域，其间具有沟道区域，用于在第一区域和第二区域之间传导电荷 地区。 第一组多条行线电连接同一行中的第二区域的单元。 多个列线电连接同一列中的第一区域的单元。 多条绑带线连接某些行线，每条绑带线电连接彼此不紧邻的第二多条行线，其中连接到第一绑带线的行线与连接到第二绑带线的行线交错 。

    Non-volatile floating gate memory cell with floating gates formed in cavities, and array thereof, and method of formation
    89.
    发明授权
    Non-volatile floating gate memory cell with floating gates formed in cavities, and array thereof, and method of formation 有权

    公开(公告)号：US06806531B1

    公开(公告)日：2004-10-19

    申请号：US10409248

    申请日：2003-04-07

    申请人： Bomy Chen ,  Dana Lee ,  Bing Yeh

    发明人： Bomy Chen ,  Dana Lee ,  Bing Yeh

    IPC分类号： H01L29788

    CPC分类号： H01L27/11521 ,  G11C16/0458 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/66825

    摘要： A non-volatile memory cell has a single crystalline semiconductive material, such as single crystalline silicon, of a first conductivity type. A first and a second region each of a second conductivity type, different from the first conductivity type, spaced apart from one another is formed in the semiconductive material. A channel region, having a first portion, and a second portion, connects the first and second regions for the conduction of charges. A dielectric is on the channel region. A floating gate, which can be conductive or non-conductive, is on the dielectric, spaced apart from the first portion of the channel region. The first portion of the channel region is adjacent to the first region, with the first floating gate having generally a triangular shape. The floating gate is formed in a cavity. A gate electrode is capacitively coupled to the first floating gate, and is spaced apart from the second portion of the channel region. The second portion of the channel region is between the first portion and the second region. A bi-directional non-volatile memory cell has two floating gates each formed in a cavity. A method of making the non-volatile memory cell and the array are also disclosed.

    Self aligned method of forming a semiconductor memory array of floating gate memory cells and a memory array made thereby
    90.
    发明授权
    Self aligned method of forming a semiconductor memory array of floating gate memory cells and a memory array made thereby 有权
    形成浮栅存储器单元的半导体存储器阵列和由此制成的存储器阵列的自对准方法

    公开(公告)号：US06329685B1

    公开(公告)日：2001-12-11

    申请号：US09401173

    申请日：1999-09-22

    申请人： Dana Lee

    发明人： Dana Lee

    IPC分类号： H01L2972

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions on the substrate substantially parallel to one another. An active region is between each pair of adjacent isolation regions. The active and isolation regions are formed in parallel and in the column direction. In the row direction, strips of spaced apart silicon nitride are formed. A source line plug is formed between adjacent pairs of silicon nitride and is in contact with a first region in the active regions, and the isolation regions. The strips of silicon nitride are removed and isotropically etched. In addition, the materials beneath the silicon nitride are also isotropically etched. Polysilicon spacers are then formed in the row direction parallel to the source line plug and adjacent to the floating gates. A second region is formed between adjacent, spaced apart, control gates. A bit line is formed in the bit line direction contacting the second region in the space between the control gates.

    摘要翻译： 在半导体衬底中形成浮动栅极存储单元的半导体存储器阵列的自对准方法在基板上具有基本上彼此平行的多个间隔开的隔离区域。 有源区域位于每对相邻隔离区域之间。 活性隔离区域和平行区域形成为平行且在列方向。 在行方向上，形成间隔开的氮化硅的条。 源极线插塞形成在相邻的氮化硅对之间并且与有源区域中的第一区域以及隔离区域接触。 去除氮化硅条并进行各向同性蚀刻。 此外，氮化硅下方的材料也被各向同性地蚀刻。 然后在平行于源极线插塞并与浮动栅极相邻的行方向上形成多晶硅间隔物。 第二区域形成在相邻的间隔开的控制门之间。 在与控制栅极之间的空间中的第二区域接触的位线方向上形成位线。