公开(公告)号：US20140179074A1

公开(公告)日：2014-06-26

申请号：US13722930

申请日：2012-12-20

申请人： Ji Pan ,  Daniel Ng ,  Sung-Shan Tai ,  Anup Bhalla

发明人： Ji Pan ,  Daniel Ng ,  Sung-Shan Tai ,  Anup Bhalla

IPC分类号： H01L21/82

CPC分类号： H01L21/26513 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/82 ,  H01L21/823412 ,  H01L27/0629 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/41766 ,  H01L29/47 ,  H01L29/4916 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872

摘要： Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)

摘要翻译： 公开了一种用于制造与肖特基二极管（MOSFET / SKY）集成的MOSFET的方法。 栅极沟槽形成在覆盖半导体衬底的外延层中，栅极材料沉积在其中。 主体，源极，电介质区域依次形成在外延层和栅极沟槽上。 通过定义源极接触深度（SCD）的电介质和源极区域，用垂直侧壁蚀刻顶部接触沟槽（TCT），所述垂直侧壁限定肖特基二极管横截面宽度SDCW; 并通过全身接触深度（TBCD）部分进入体区。 身体接触深度（BCD）

公开(公告)号：US08748268B1

公开(公告)日：2014-06-10

申请号：US13722930

申请日：2012-12-20

申请人： Ji Pan ,  Daniel Ng ,  Sung-Shan Tai ,  Anup Bhalla

发明人： Ji Pan ,  Daniel Ng ,  Sung-Shan Tai ,  Anup Bhalla

IPC分类号： H01L21/336

CPC分类号： H01L21/26513 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/82 ,  H01L21/823412 ,  H01L27/0629 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/41766 ,  H01L29/47 ,  H01L29/4916 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872

摘要： Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)

摘要翻译： 公开了一种用于制造与肖特基二极管（MOSFET / SKY）集成的MOSFET的方法。 栅极沟槽形成在覆盖半导体衬底的外延层中，栅极材料沉积在其中。 主体，源极，电介质区域依次形成在外延层和栅极沟槽上。 通过定义源极接触深度（SCD）的电介质和源极区域，用垂直侧壁蚀刻顶部接触沟槽（TCT），所述垂直侧壁限定肖特基二极管横截面宽度SDCW; 并通过全身接触深度（TBCD）部分进入体区。 身体接触深度（BCD）

公开(公告)号：US08643071B2

公开(公告)日：2014-02-04

申请号：US13517770

申请日：2012-06-14

申请人： Ji Pan ,  Daniel Ng ,  Anup Bhalla

发明人： Ji Pan ,  Daniel Ng ,  Anup Bhalla

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/7803 ,  H01L29/7805 ,  H01L29/94 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

摘要： A MOSFET device includes one or more active device structures and one or more dummy structures formed from semiconductor drift region and body regions. The dummy structures are electrically connected in parallel to the active device structures. Each dummy structure includes an electrically insulated snubber electrode formed proximate the body region and the drift region, an insulator portion formed over the snubber electrode and a top surface of the body region, and one or more electrical connections between the snubber electrode and portions of the body region and a source electrode. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： MOSFET器件包括一个或多个有源器件结构和由半导体漂移区域和主体区域形成的一个或多个虚设结构。 虚拟结构与有源器件结构并联电连接。 每个虚拟结构包括在主体区域和漂移区域附近形成的电绝缘缓冲电极，形成在缓冲电极上的绝缘体部分和身体区域的顶表面，以及缓冲电极和部分之间的一个或多个电连接 体区和源电极。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US20130334599A1

公开(公告)日：2013-12-19

申请号：US13517770

申请日：2012-06-14

申请人： Ji Pan ,  Daniel Ng ,  Anup Bhalla

发明人： Ji Pan ,  Daniel Ng ,  Anup Bhalla

IPC分类号： H01L27/088 ,  H01L21/8232

CPC分类号： H01L29/7813 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/7803 ,  H01L29/7805 ,  H01L29/94 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

摘要： A MOSFET device includes one or more active device structures and one or more dummy structures formed from semiconductor drift region and body regions. The dummy structures are electrically connected in parallel to the active device structures. Each dummy structure includes an electrically insulated snubber electrode formed proximate the body region and the drift region, an insulator portion formed over the snubber electrode and a top surface of the body region, and one or more electrical connections between the snubber electrode and portions of the body region and a source electrode. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： MOSFET器件包括一个或多个有源器件结构和由半导体漂移区域和主体区域形成的一个或多个虚设结构。 虚拟结构与有源器件结构并联电连接。 每个虚拟结构包括在主体区域和漂移区域附近形成的电绝缘缓冲电极，形成在缓冲电极上的绝缘体部分和身体区域的顶表面，以及缓冲电极和部分之间的一个或多个电连接 体区和源电极。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US08502302B2

公开(公告)日：2013-08-06

申请号：US13098852

申请日：2011-05-02

申请人： Yi Su ,  Daniel Ng ,  Anup Bhalla ,  Hong Chang ,  Jongoh Kim ,  John Chen

发明人： Yi Su ,  Daniel Ng ,  Anup Bhalla ,  Hong Chang ,  Jongoh Kim ,  John Chen

IPC分类号： H01L27/06 ,  H01L21/336

CPC分类号： H01L29/7801 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0891 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/47 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/782 ,  H01L29/872

摘要： A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.

摘要翻译： 半导体器件包括多个沟槽，包括有源区域中的有源栅极沟槽和栅极流道/终止沟槽以及在有源区域外部的终止区域中的屏蔽电极拾取沟槽。 栅极流道/终止沟槽包括限定位于有源区域之外的台面的一个或多个沟槽。 在多个沟槽中形成第一导电区域。 在限定台面的沟槽中形成中间介质区域和端接保护区域。 在限定台面的沟槽部分中形成第二导电区域。 第二导电区域通过中间介电区域与第一导电区域电隔离。 对第二导电区域进行第一电接触，并且在屏蔽电极拾取沟槽中对第一导电区域进行第二电接触。 在台面内形成一个或多个肖特基二极管。

公开(公告)号：US08362585B1

公开(公告)日：2013-01-29

申请号：US13184488

申请日：2011-07-15

申请人： Anup Bhalla ,  Ji Pan ,  Daniel Ng

发明人： Anup Bhalla ,  Ji Pan ,  Daniel Ng

IPC分类号： H01L29/66 ,  H01L29/40 ,  H01L21/02

CPC分类号： H01L29/872 ,  H01L24/05 ,  H01L29/0619 ,  H01L29/417 ,  H01L2924/01029 ,  H01L2924/12032 ,  H01L2924/00

摘要： A semiconductor junction barrier Schottky (JBS-SKY) diode with enforced upper contact structure (EUCS) is disclosed. Referencing an X-Y-Z coordinate, the JBS-SKY diode has semiconductor substrate (SCST) parallel to X-Y plane. Active device zone (ACDZ) atop SCST and having a JBS-SKY diode with Z-direction current flow. Peripheral guarding zone (PRGZ) atop SCST and surrounding the ACDZ. The ACDZ has active lower semiconductor structure (ALSS) and enforced active upper contact structure (EUCS) atop ALSS. The EUC has top contact metal (TPCM) extending downwards and in electrical conduction with bottom of EUCS; and embedded bottom supporting structure (EBSS) inside TPCM and made of a hard material, the EBSS extending downwards till bottom of the EUCS. Upon encountering bonding force onto TPCM during packaging of the JBS-SKY diode, the EBSS enforces the EUCS against an otherwise potential micro cracking of the TPCM degrading the leakage current of the JBS-SKY diode.

摘要翻译： 公开了一种具有强制上接触结构（EUCS）的半导体结屏障肖特基（JBS-SKY）二极管。 参考X-Y-Z坐标，JBS-SKY二极管具有与X-Y平面平行的半导体衬底（SCST）。 有源器件区（ACDZ）位于SCST上方，并具有Z方向电流流动的JBS-SKY二极管。 外围防护区（PRGZ）在SCST顶部并围绕ACDZ。 ACDZ在ALSS顶部具有活性较低的半导体结构（ALSS）和强制性的上接触结构（EUCS）。 EUC具有向下延伸并与EUCS底部导电的顶部接触金属（TPCM）; 并在TPCM内部嵌入底部支撑结构（EBSS），由硬质材料制成，EBSS向下延伸至EUCS底部。 在JBS-SKY二极管封装期间遇到TPCM上的结合力时，EBSS强制EUCS抵抗TPCM的另外潜在的微裂纹，降低JBS-SKY二极管的漏电流。

公开(公告)号：US08304315B2

公开(公告)日：2012-11-06

申请号：US13149051

申请日：2011-05-31

申请人： Yi Su ,  Anup Bhalla ,  Daniel Ng

发明人： Yi Su ,  Anup Bhalla ,  Daniel Ng

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/66734 ,  H01L29/7815 ,  H01L2224/0603 ,  H01L2924/13091 ,  H01L2924/00

摘要： A main FET and one or more sense FETs are formed in a common substrate. The main FET and sense FET(s) include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and sense FET(s). An electrical isolation may be between the gate terminals of the main FET and the sense FET(s). A sense pad in electrical contact with the source of the one or more sense FETs does not overlap an area of the device containing the sense FET(s). It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 主FET和一个或多个感测FET形成在公共衬底中。 主FET和感测FET包括源极端子，栅极端子和漏极端子。 公共栅极焊盘连接主FET和检测FET的栅极端子。 电隔离可以在主FET的栅极端子和感测FET之间。 与一个或多个感测FET的源极电接触的感测焊盘不与包含感测FET的器件的区域重叠。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US08174283B2

公开(公告)日：2012-05-08

申请号：US12454004

申请日：2009-05-11

申请人： Anup Bhalla ,  Sik K. Lui ,  Daniel Ng

发明人： Anup Bhalla ,  Sik K. Lui ,  Daniel Ng

IPC分类号： G01R31/02 ,  H01L21/66

CPC分类号： H04L63/102 ,  G01R31/2625 ,  G01R31/2884 ,  G01R35/005 ,  H01L22/14 ,  H01L2924/0002 ,  H04L63/08 ,  H01L2924/00

摘要： This invention discloses a method for calibrating a gate resistance measurement of a semiconductor power device that includes a step of forming a RC network on a test area on a semiconductor wafer adjacent to a plurality of semiconductor power chips and measuring a resistance and a capacitance of the RC network to prepare for carrying out a wafer-level measurement calibration of the semiconductor power device. The method further includes a step of connecting a probe card to a set of contact pads on the semiconductor wafer for carrying out the wafer-level measurement calibration followed by performing a gate resistance Rg measurement for the semiconductor power chips.

摘要翻译： 本发明公开了一种用于校准半导体功率器件的栅极电阻测量的方法，包括在与多个半导体功率芯片相邻的半导体晶片上的测试区域上形成RC网络的步骤，并测量电阻和电容 RC网络，准备进行半导体功率器件的晶圆级测量校准。 该方法还包括将探针卡连接到半导体晶片上的一组接触焊盘，以执行晶片级测量校准，然后对半导体功率芯片执行栅极电阻Rg测量。

公开(公告)号：US07659570B2

公开(公告)日：2010-02-09

申请号：US11125506

申请日：2005-05-09

申请人： Anup Bhalla ,  Daniel Ng ,  Tiesheng Li ,  Sik K. Lui

发明人： Anup Bhalla ,  Daniel Ng ,  Tiesheng Li ,  Sik K. Lui

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/66712 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7827

摘要： This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.

摘要翻译： 本发明公开了一种支撑在半导体上的新开关装置，其包括设置在第一表面上的漏极和设置在与第一表面相对的所述半导体的第二表面附近的源极区域。 开关装置还包括设置在第二表面顶部的用于控制源极到漏极电流的绝缘栅电极。 开关装置还包括插入到绝缘栅电极中的源电极，用于基本上防止栅电极和绝缘栅电极下方的外延区之间的电场的耦合。 源电极进一步覆盖并延伸在绝缘栅上，以覆盖半导体的第二表面上的区域以接触源区。 半导体衬底还包括设置在漏极区以上且具有与漏极区不同的掺杂浓度的外延层。 绝缘栅电极还包括用于使栅电极与源电极绝缘的绝缘层，其中绝缘层的厚度取决于垂直功率器件的Vgsmax等级。

公开(公告)号：US20060202264A1

公开(公告)日：2006-09-14

申请号：US11413249

申请日：2006-04-29

申请人： Anup Bhalla ,  Daniel Ng ,  Sik Lui

发明人： Anup Bhalla ,  Daniel Ng ,  Sik Lui

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells and a junction barrier Schottky (JBS) area. The semiconductor power device includes the JBS area that further includes a plurality of Schottky diodes each having a PN junction disposed on an epitaxial layer near a top surface of a semiconductor substrate wherein the PN junction further includes a counter dopant region disposed in the epitaxial layer for reducing a sudden reversal of dopant profile near the PN junction for preventing an early breakdown in the PN junction.

摘要翻译： 本发明公开了一种半导体功率器件，其包括具有多个功率晶体管单元和接合势垒肖特基（JBS）区域的有源单元区域。 半导体功率器件包括JBS区域，其还包括多个肖特基二极管，每个肖特基二极管各自具有设置在半导体衬底的顶表面附近的外延层上的PN结，其中PN结还包括设置在外延层中的反掺杂剂区域 减少PN结附近的掺杂剂分布的突然反转，以防止PN结中的早期击穿。