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公开(公告)号：US20160126454A1
公开(公告)日：2016-05-05
申请号：US14991660
申请日：2016-01-08
Applicant: Everspin Technologies, Inc.
Inventor： Chaitanya Mudivarthi , Sarin A. Deshpande , Sanjeev Aggarwal
CPC classification number: H01L43/12 , G11B5/3163 , G11C11/161 , H01L27/222 , H01L27/228 , H01L43/02 , H01L43/08 , Y10T29/49021
Abstract: Methods for manufacturing magnetoresistive devices are presented in which isolation of magnetic layers in the magnetoresistive stack is achieved by oxidizing exposed sidewalls of the magnetic layers prior to subsequent etching steps. Etching the magnetic layers using a non-reactive gas further prevents degradation of the sidewalls.
Abstract translation: 介绍制造磁阻器件的方法，其中通过在随后的蚀刻步骤之前氧化暴露的磁性层的侧壁来实现磁阻堆叠中的磁层的隔离。 使用非反应性气体蚀刻磁性层进一步防止侧壁的劣化。
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公开(公告)号：US09269891B2
公开(公告)日：2016-02-23
申请号：US13972637
申请日：2013-08-21
Applicant: EverSpin Technologies, Inc.
Inventor： Renu Whig , Philip Mather , Kenneth Smith , Sanjeev Aggarwal , Jon Slaughter , Nicholas Rizzo
CPC classification number: H01L43/12 , B82Y25/00 , G01R33/0052 , G01R33/09 , G01R33/093 , G01R33/098 , H01L27/22 , H01L43/02 , H01L43/08
Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.
Abstract translation: 半导体工艺集成了三个桥接电路，每个电路包括在单个芯片上作为惠斯登电桥耦合的磁阻传感器，以在三个正交方向上感测磁场。 该过程包括形成磁阻传感器的各种沉积和蚀刻步骤以及在三个桥接电路中的一个上的多个通量引导器，用于将“Z”轴磁场传送到在XY平面中定向的传感器上。
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公开(公告)号：US20150380640A1
公开(公告)日：2015-12-31
申请号：US14845697
申请日：2015-09-04
Applicant: Everspin Technologies, Inc.
Inventor： Sarin Deshpande , Sanjeev Aggarwal
IPC: H01L43/12
CPC classification number: H01L43/12 , G11B5/84 , G11C11/161 , H01L27/222 , H01L43/02 , H01L43/08
Abstract: A method of manufacturing a magnetoresistive-based device using a plurality of hard masks. The magnetoresistive-based device includes magnetic material layers formed between a first electrically conductive layer and a second electrically conductive layer, the magnetic materials layers including a tunnel barrier layer formed between a first magnetic materials layer and a second magnetic materials layer. In one embodiment, the method may include removing the first electrically conductive layer and the first magnetic materials layer unprotected by a first hard mask, to form a first electrode and a first magnetic materials, respectively, and removing the tunnel barrier layer and the second magnetic materials layer unprotected by a second hard mask to form a tunnel barrier and second magnetic materials, and the second electrically conductive layer unprotected by the second hard mask to form, and a second electrode.
Abstract translation: 使用多个硬掩模制造基于磁阻的装置的方法。 基于磁阻的器件包括在第一导电层和第二导电层之间形成的磁性材料层，所述磁性材料层包括在第一磁性材料层和第二磁性材料层之间形成的隧道势垒层。 在一个实施例中，该方法可以包括移除未被第一硬掩模保护的第一导电层和第一磁性材料层，以分别形成第一电极和第一磁性材料，并且去除隧道势垒层和第二磁性层 材料层不被第二硬掩模保护以形成隧道势垒和第二磁性材料，以及由第二硬掩模未被保护以形成的第二导电层和第二电极。
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公开(公告)号：US09166155B2
公开(公告)日：2015-10-20
申请号：US14264520
申请日：2014-04-29
Applicant: Everspin Technologies, Inc.
Inventor： Sarin A. Deshpande , Sanjeev Aggarwal
CPC classification number: H01L43/12 , G11B5/84 , G11C11/161 , H01L27/222 , H01L43/02 , H01L43/08
Abstract: A method of manufacturing a magnetoresistive-based device having magnetic material layers formed between a first electrically conductive layer and a second electrically conductive layer, the magnetic materials layers including a tunnel barrier layer formed between a first magnetic materials layer and a second magnetic materials layer, including removing the first electrically conductive layer and the first magnetic materials layer unprotected by a first hard mask, to form a first electrode and a first magnetic materials, respectively; and removing the tunnel barrier layer, second magnetic materials layer, and second electrically conductive layer unprotected by the second hard mask to form a tunnel barrier, second magnetic materials, and a second electrode.
Abstract translation: 一种制造具有在第一导电层和第二导电层之间形成的磁性材料层的基于磁阻的器件的方法，所述磁性材料层包括在第一磁性材料层和第二磁性材料层之间形成的隧道势垒层， 包括去除未被第一硬掩模保护的第一导电层和第一磁性材料层，分别形成第一电极和第一磁性材料; 以及去除不受第二硬掩模保护的隧道势垒层，第二磁性材料层和第二导电层，以形成隧道势垒，第二磁性材料和第二电极。
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公开(公告)号：US20150236254A1
公开(公告)日：2015-08-20
申请号：US14704915
申请日：2015-05-05
Applicant: Everspin Technologies, Inc.
Inventor： Kerry Joseph Nagel , Kenneth Smith , Moazzem Hossain , Sanjeev Aggarwal
IPC: H01L43/12 , H01L43/08 , H01L21/285 , H01L21/768 , H01L21/3213 , H01L43/02 , H01L27/22
CPC classification number: H01L43/12 , H01L21/28568 , H01L21/32133 , H01L21/76819 , H01L21/7684 , H01L21/76877 , H01L27/222 , H01L27/226 , H01L27/228 , H01L43/02 , H01L43/08
Abstract: A conductive via disposed beneath a magnetic device and aligned therewith. In certain embodiments, an electrode formed on the conductive via may be polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to, for example, a 45 nanometer node.
Abstract translation: 导电通孔，其设置在磁性装置的下方并与其对准。 在某些实施例中，形成在导电通孔上的电极可以被抛光以消除起始于导电通孔的步骤功能或接缝，以向上传播通过各种沉积层。 该集成方法允许将MRAM设备改进为例如45纳米节点。
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Patent Agency Ranking
86.发明授权公开(公告)号：US09093640B2
公开(公告)日：2015-07-28
申请号：US14219902
申请日：2014-03-19
Applicant: Everspin Technologies, Inc.
Inventor： Sanjeev Aggarwal , Kerry Nagel , Jason Janesky
IPC: H01L43/12
CPC classification number: H01L43/12 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/10
Abstract: A dual tunnel barrier magnetic element has a free magnetic layer positioned between first and second tunnel barriers and an electrode over the second tunnel barrier. A two step etch process allows for forming an encapsulation material on a side wall of the electrode and the second tunnel barrier subsequent to the first etch for preventing damage to the first tunnel barrier when performing the second etch to remove a portion of the free layer.
Abstract translation: 双隧道屏障磁性元件具有位于第一和第二隧道屏障之间的自由磁性层和位于第二隧道屏障上的电极。 两步蚀刻工艺允许在第一次蚀刻之后在电极的侧壁上形成封装材料，并且在进行第二蚀刻以去除自由层的一部分时防止第一隧道势垒的损坏。
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87.发明授权公开(公告)号：US11925122B2
公开(公告)日：2024-03-05
申请号：US17468896
申请日：2021-09-08
Applicant: Everspin Technologies, Inc.
Inventor： Sanjeev Aggarwal , Kerry Nagel , Jason Janesky
CPC classification number: H10N50/01 , G11C11/161 , H10N50/10 , H10N50/80 , H10N50/85
Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.
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公开(公告)号：US11798646B2
公开(公告)日：2023-10-24
申请号：US17512392
申请日：2021-10-27
Applicant: Everspin Technologies, Inc.
Inventor： Syed M. Alam , Jason Janesky , Han Kyu Lee , Hamid Almasi , Pedro Sanchez , Cristian P. Masgras , Iftekhar Rahman , Sumio Ikegawa , Sanjeev Aggarwal , Dimitri Houssameddine , Frederick Charles Neumeyer
CPC classification number: G11C29/42 , G11C29/1201 , G11C29/18 , G11C29/4401 , G11C2029/0407 , G11C2029/1202
Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.
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公开(公告)号：US11778919B2
公开(公告)日：2023-10-03
申请号：US17510818
申请日：2021-10-26
Applicant: Everspin Technologies, Inc.
Inventor： Sarin A. Deshpande , Kerry Joseph Nagel , Chaitanya Mudivarthi , Sanjeev Aggarwal
Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
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公开(公告)号：US10971545B2
公开(公告)日：2021-04-06
申请号：US16245783
申请日：2019-01-11
Applicant: Everspin Technologies, Inc.
Inventor： Sanjeev Aggarwal , Kevin Conley , Sarin A. Deshpande
IPC: H01L27/22 , G11C5/06 , G11C5/08 , G11C11/16 , H01F10/32 , H01F41/34 , H01L21/768 , H01L23/522 , H01L23/528 , H01L43/02 , H01L43/12
Abstract: A magnetoresistive device may include multiple magnetic tunnel junction (MTJ) stacks separated from each other by one or more dielectric material layers and electrically conductive vias extending through the one more dielectric material layers. Each MTJ stack may include multiple MTJ bits arranged one on top of another and the electrically conductive vias may be configured to electrically access each MTJ bit of the multiple MTJ stacks.
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