公开(公告)号：US10832965B2

公开(公告)日：2020-11-10

申请号：US15868229

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yiheng Xu ,  Haiting Wang ,  Qun Gao ,  Scott Beasor ,  Kyung Bum Koo ,  Ankur Arya

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/161 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105

Abstract: Integrated circuit devices include trenches in a material layer that divide the material layer into fins. With such devices, an insulator partially fills the trenches and contacts the material layer. The top surface of the insulator (e.g., the surface opposite where the insulator contacts the material layer) has a convex dome shape between at least two of the fins. The dome shape has a first thickness from (from the bottom of the trench) where the insulator contacts the fins, and a second thickness that is greater than the first thickness where the insulator is between the fins. Further, there is a maximum thickness difference between the first and second thicknesses at the midpoint between the fins (e.g., the highest point of the dome shape is at the midpoint between the fins). Also, the top surface of the first insulator has concave divots where the first insulator contacts the fins.

公开(公告)号：US10818659B2

公开(公告)日：2020-10-27

申请号：US16161294

申请日：2018-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Hui Zang ,  Guowei Xu ,  Scott Beasor

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction, and parallel gate structures intersect the fins in a second direction perpendicular to the first direction. Also, source/drain structures are positioned on the fins between the gate structures, source/drain contacts are positioned on the source/drain structures, sidewall insulators are positioned between the gate structures and the source/drain contacts (wherein the sidewall insulators have a lower portion adjacent to the fins and an upper portion distal to the fins), and upper sidewall spacers are positioned between the upper portion of the sidewall insulators and the source/drain contacts.

公开(公告)号：US10714376B2

公开(公告)日：2020-07-14

申请号：US16016910

申请日：2018-06-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chih-Chiang Chang ,  Haifeng Sheng ,  Jiehui Shu ,  Haigou Huang ,  Pei Liu ,  Jinping Liu ,  Haiting Wang ,  Daniel J. Jaeger

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768

Abstract: The present disclosure relates to methods for forming fill materials in trenches having different widths and related structures. A method may include: forming a first fill material in a first and second trench where the second trench has a greater width than the first trench; removing a portion of the first fill material from each trench and forming a second fill material over the first fill material; removing a portion of the first and second fill material within the second trench; and forming a third fill material in the second trench. The structure may include a first fill material in trenches having different widths wherein the upper surfaces of the first fill material in each trench are substantially co-planar. The structure may also include a second fill material on the first fill material in each trench, the second fill material having a substantially equal thickness in each trench.

公开(公告)号：US10651173B1

公开(公告)日：2020-05-12

申请号：US16204506

申请日：2018-11-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guowei Xu ,  Hui Zang ,  Ruilong Xie ,  Haiting Wang

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures composed of semiconductor material; a plurality of replacement gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of replacement gate structures; and a single diffusion break between the diffusion regions of the adjacent replacement gate structures, the single diffusion break being filled with an insulator material. In a first cross-sectional view, the single diffusion break extends into the semiconductor material and in a second cross-sectional view, the single diffusion break is devoid of semiconductor material of the plurality of fin structures.

公开(公告)号：US20200119000A1

公开(公告)日：2020-04-16

申请号：US16161294

申请日：2018-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Hui Zang ,  Guowei Xu ,  Scott Beasor

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51

Abstract: Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction, and parallel gate structures intersect the fins in a second direction perpendicular to the first direction. Also, source/drain structures are positioned on the fins between the gate structures, source/drain contacts are positioned on the source/drain structures, sidewall insulators are positioned between the gate structures and the source/drain contacts (wherein the sidewall insulators have a lower portion adjacent to the fins and an upper portion distal to the fins), and upper sidewall spacers are positioned between the upper portion of the sidewall insulators and the source/drain contacts.

公开(公告)号：US20200091005A1

公开(公告)日：2020-03-19

申请号：US16134708

申请日：2018-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qun Gao ,  Balaji Kannan ,  Shesh Mani Pandey ,  Haiting Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: A method of forming a gate structure with an undercut region includes, among other things, forming a plurality of fins above a substrate and an isolation structure above the substrate and between the plurality of fins, forming a placeholder gate structure above the plurality of fins in a first region and above the isolation structure in a second region, selectively removing a portion of the placeholder structure in the second region to define an undercut recess, forming a spacer structure adjacent the sacrificial gate structure, forming a dielectric layer adjacent the spacer structure and in the undercut recess, removing remaining portions of the placeholder gate structure to define a gate cavity, and forming a replacement gate structure in the gate cavity.

公开(公告)号：US10593757B2

公开(公告)日：2020-03-17

申请号：US15961912

申请日：2018-04-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Ruilong Xie ,  Hui Zang ,  Haiting Wang

IPC: H01L29/08 ,  H01L29/78 ,  C30B29/40 ,  H01L29/66 ,  H01L21/02 ,  C30B25/04

Abstract: Methods form an integrated circuit structure that includes complementary transistors on a first layer. An isolation structure is between the complementary transistors. Each of the complementary transistors includes source/drain regions and a gate conductor between the source/drain regions, and insulating spacers are between the gate conductor and the source/drain regions in each of the complementary transistors. With these methods and structures, an etch stop layer is formed only on the source/drain regions.

公开(公告)号：US10586860B2

公开(公告)日：2020-03-10

申请号：US15970217

申请日：2018-05-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Laertis Economikos ,  Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Hui Zhan ,  Tao Han ,  Haiting Wang ,  Jinping Liu ,  Hui Zang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/3065

Abstract: In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

公开(公告)号：US20200066588A1

公开(公告)日：2020-02-27

申请号：US16112511

申请日：2018-08-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Guowei Xu ,  Haiting Wang

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/06 ,  H01L29/49 ,  H01L23/535 ,  H01L23/532 ,  H01L29/66

Abstract: A method, apparatus, and manufacturing system are disclosed for a fin field effect transistor having a reduced risk of short circuits between a gate and a source/drain contact. In one embodiment, we disclose a semiconductor device including a fin structure comprising a fin body, source/drain regions, and a metal formation disposed above the source/drain regions, wherein the metal formation has a first height; and a gate structure between the source/drain regions, wherein each gate structure comprises spacers in contact with the metal formation, wherein the spacers have a second height less than the first height, a metal plug between the spacers and below the second height, and a T-shaped cap above the metal plug and having the first height.

公开(公告)号：US20200027979A1

公开(公告)日：2020-01-23

申请号：US16038384

申请日：2018-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Chung Foong Tan ,  Guowei Xu ,  Haiting Wang ,  Yue Zhong ,  Ruilong Xie ,  Tek Po Rinus Lee ,  Scott Beasor

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/306 ,  H01L29/66 ,  H01L29/08

Abstract: One illustrative method disclosed herein includes forming a low-k sidewall spacer adjacent opposing sidewalls of a gate structure, forming contact etch stop layers (CESLs) adjacent the low-k sidewall spacer in the source/drain regions of the transistor, and forming a first insulating material above the CESLs. In this example, the method also includes recessing the first insulating material so as to expose substantially vertically oriented portions of the CESLs, removing a portion of a lateral width of the substantially vertically oriented portions of the CESLs so as to form trimmed CESLs, and forming a high-k spacer on opposite sides of the gate structure, wherein at least a portion of the high-k spacer is positioned laterally adjacent the trimmed substantially vertically oriented portions of the trimmed CESLs.