公开(公告)号：US5745417A

公开(公告)日：1998-04-28

申请号：US661930

申请日：1996-06-11

申请人： Shinichi Kobayashi ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Takeshi Nakayama ,  Tomoshi Futatsuya ,  Natsuo Ajika ,  Yuichi Kunori ,  Hiroshi Onoda ,  Atsushi Fukumoto ,  Makoto Ohi

发明人： Shinichi Kobayashi ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Takeshi Nakayama ,  Tomoshi Futatsuya ,  Natsuo Ajika ,  Yuichi Kunori ,  Hiroshi Onoda ,  Atsushi Fukumoto ,  Makoto Ohi

IPC分类号： G11C16/04 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  G11C7/00

CPC分类号： H01L27/11517 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/16 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546 ,  H01L29/7883

摘要： In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.

公开(公告)号：US5538912A

公开(公告)日：1996-07-23

申请号：US370755

申请日：1995-01-10

申请人： Yuichi Kunori ,  Natsuo Ajika ,  Hiroshi Onoda ,  Makoto Ohi ,  Atsushi Fukumoto

发明人： Yuichi Kunori ,  Natsuo Ajika ,  Hiroshi Onoda ,  Makoto Ohi ,  Atsushi Fukumoto

IPC分类号： H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/10844 ,  H01L27/105 ,  H01L27/11517 ,  H01L27/11526

摘要： In a semiconductor memory device according to the present invention, a conductive layer is formed on a field oxide film in a boundary region on the main surface of a semiconductor substrate. A floating gate electrode, an interlayer insulating film, and a control gate electrode are formed on the semiconductor substrate in a memory cell array region with a gate insulating film interposed therebetween. A gate electrode is formed in a peripheral circuit region with the gate insulating film interposed therebetween. An interlayer insulating film is formed on the conductive layer, the gate electrode, and the control gate electrode. A contact hole is formed at a predetermined position of the interlayer insulating film. An interconnection layer is selectively formed on the interlayer insulating film including the inner surface of the contact hole. According to the present invention, it is possible to prevent formation of a concave portion on the surface of the field oxide film in the boundary region. It is also possible to protect the memory cell array region from an external noise by forming the conductive layer on the field oxide film in the boundary region and by fixing the potential of the conductive layer.

摘要翻译： 在根据本发明的半导体存储器件中，在半导体衬底的主表面上的边界区域中的场氧化物膜上形成导电层。 在半导体衬底上形成有一个栅极绝缘膜和一个控制栅电极的存储单元阵列区域中，栅极绝缘膜插在其间。 栅极电极形成在外围电路区域中，栅极绝缘膜插入其间。 在导电层，栅电极和控制栅电极上形成层间绝缘膜。 在层间绝缘膜的预定位置处形成接触孔。 在包括接触孔的内表面的层间绝缘膜上选择性地形成布线层。 根据本发明，可以防止在边界区域的场氧化膜的表面上形成凹部。 也可以通过在边界区域的场氧化膜上形成导电层，并通过固定导电层的电位来保护存储单元阵列区域免受外部噪声的影响。

公开(公告)号：US5347151A

公开(公告)日：1994-09-13

申请号：US797888

申请日：1991-11-26

申请人： Masahiro Shimizu ,  Takehisa Yamaguchi ,  Natsuo Ajika

发明人： Masahiro Shimizu ,  Takehisa Yamaguchi ,  Natsuo Ajika

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L23/00

CPC分类号： H01L27/10808

摘要： Access transistors of memory cells in a DRAM are formed in a solid phrase epitaxial single crystalline layer on the surface of a silicon substrate. A bit line extending over the surface of an element isolation and insulation film is formed by patterning a polycrystalline silicon layer extending to the single crystalline silicon layer as a layer. A stacked capacitor is connected to one source/drain of the access transistor through a conductive layer extending to the single crystalline silicon layer and over a field oxide film. Part of the stacked capacitor extends over the bit line. The connection region of the bit line, the capacitor and the source/drain is formed above the element isolation and insulation film, so that the source/drain region of the access transistor can be reduced.

摘要翻译： DRAM中的存储单元的存取晶体管形成在硅衬底的表面上的固体短边外延单晶层中。 在元件隔离和绝缘膜的表面上延伸的位线是通过将延伸到单晶硅层的多晶硅层图案化为一层而形成的。 叠层电容器通过延伸到单晶硅层和场氧化物膜上的导电层连接到存取晶体管的一个源极/漏极。 堆叠电容器的一部分在位线上延伸。 位线，电容器和源极/漏极的连接区域形成在元件隔离和绝缘膜上方，从而可以减小存取晶体管的源极/漏极区域。

公开(公告)号：US5341028A

公开(公告)日：1994-08-23

申请号：US770041

申请日：1991-10-03

申请人： Yasuo Yamaguchi ,  Natsuo Ajika ,  Tsuyoshi Yamano

发明人： Yasuo Yamaguchi ,  Natsuo Ajika ,  Tsuyoshi Yamano

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/762 ,  H01L27/092 ,  H01L27/12 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L29/786 ,  H01L27/01 ,  H01L23/48 ,  H01L27/02 ,  H01L29/10

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/78621 ,  H01L21/76267 ,  H01L21/76281 ,  H01L2924/0002 ,  Y10S257/90

摘要： A semiconductor device of a field effect transistor having an SOI structure is formed as below. Using a gate electrode 20 as a mask, n type impurities are implanted into an SOI layer of p type to form additional source/drain regions of intermediate concentration. Then, a relatively thin sidewall spacer is formed at the sidewall of the gate electrode. Using the sidewall spacer as a mask, a titanium silicide layer is formed in self-alignment on the surface of the SOI layer. Next, a relatively thick sidewall spacer is formed. Using this sidewall spacer as a mask, n type impurities are implanted to form a source/drain region of high concentration. According to this manufacturing step, over-etching of the source/drain region are prevented in performing anisotropic etching at the time of sidewall spacer formation.

摘要翻译： 如下形成具有SOI结构的场效晶体管的半导体器件。 使用栅电极20作为掩模，将n型杂质注入到p型SOI层中以形成中等浓度的附加源/漏区。 然后，在栅电极的侧壁处形成相对薄的侧壁间隔物。 使用侧壁间隔物作为掩模，在SOI层的表面上自对准地形成硅化钛层。 接下来，形成相对较厚的侧壁间隔物。 使用该侧壁间隔物作为掩模，注入n型杂质以形成高浓度的源/漏区。 根据该制造步骤，在侧壁间隔物形成时，在进行各向异性蚀刻时，防止了源极/漏极区域的过度蚀刻。

公开(公告)号：US5275629A

公开(公告)日：1994-01-04

申请号：US762355

申请日：1991-09-19

申请人： Natsuo Ajika ,  Masahiro Shimizu ,  Takehisa Yamaguchi

发明人： Natsuo Ajika ,  Masahiro Shimizu ,  Takehisa Yamaguchi

IPC分类号： G01J1/28 ,  C23C16/48 ,  H01L21/00 ,  H01L21/205 ,  H01L21/285 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/66 ,  C23C16/00

CPC分类号： H01L21/67115 ,  C23C16/481 ,  Y10T29/41

摘要： A semiconductor device manufacturing apparatus has a first space and a second space in a process chamber in which a semiconductor wafer is accommodated, the first and second spaces being separated by the semiconductor wafer. A process gas port opens into the first space adjacent to the obverse surface of the semiconductor wafer, and an infrared light transmission window is formed in a wall of the chamber at the second space facing the reverse surface of the semiconductor wafer. No layers are deposited on the reverse surface of the semiconductor wafer and the infrared light transmission window so that the emissivity at the reverse surface of the semiconductor wafer is not changed during layer deposition. The temperature during processing can therefore be monitored accurately with a pyrometer, and a reduction in the transmissivity of the window is prevented.

摘要翻译： 半导体器件制造装置在其中容纳有半导体晶片的处理室中具有第一空间和第二空间，第一和第二空间被半导体晶片隔开。 处理气体通道向与半导体晶片的正面相邻的第一空间开口，并且在面向半导体晶片的背面的第二空间处，在室的壁上形成红外光透射窗。 在半导体晶片和红外光透射窗的反面上没有层沉积，使得在层沉积期间半导体晶片的反面的发射率不变。 因此，可以用高温计精确地监测加工过程中的温度，并且防止窗口的透射率的降低。