公开(公告)号：US07892958B2

公开(公告)日：2011-02-22

申请号：US12422849

申请日：2009-04-13

申请人： Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Seong-Geon Park ,  Taek-Soo Jeon

发明人： Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Seong-Geon Park ,  Taek-Soo Jeon

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a polysilicon layer contacts a gate insulation film while the other transistor includes a gate structure in which a metal layer contacts a gate insulation film.

摘要翻译： 半导体器件具有彼此不同结构的两个晶体管。 晶体管中的一个是P型，另一个是N型。 一个晶体管包括其中多晶硅层接触栅极绝缘膜的栅极结构，而另一个晶体管包括其中金属层与栅极绝缘膜接触的栅极结构。

公开(公告)号：US20100240180A1

公开(公告)日：2010-09-23

申请号：US12725743

申请日：2010-03-17

申请人： In-Sang Jeon ,  Si-Hyung Lee ,  Jong-Ryeol Yoo ,  Yu-Gyun Shin ,  Suk-Hun Choi

发明人： In-Sang Jeon ,  Si-Hyung Lee ,  Jong-Ryeol Yoo ,  Yu-Gyun Shin ,  Suk-Hun Choi

IPC分类号： H01L21/336 ,  H01L21/8242

CPC分类号： H01L29/4236 ,  H01L21/67207 ,  H01L21/823437 ,  H01L21/823456 ,  H01L29/66621 ,  H01L29/78

摘要： In a method of manufacturing a semiconductor device, a recess is formed in an active region of a substrate. A gate insulation layer is formed in the first recess. A barrier layer is formed on the gate insulation layer. A preliminary nucleation layer having a first resistance is formed on the barrier layer. The preliminary nucleation layer is converted into a nucleation layer having a second resistance substantially smaller than the first resistance. A conductive layer is formed on the nucleation layer. The conductive layer, the nucleation layer, the barrier layer and the gate insulation layer are partially etched to form a buried gate structure including a gate insulation layer pattern, a barrier layer pattern, a nucleation layer pattern and a conductive layer pattern.

摘要翻译： 在制造半导体器件的方法中，在衬底的有源区中形成凹部。 在第一凹部中形成栅极绝缘层。 在栅绝缘层上形成阻挡层。 在阻挡层上形成具有第一电阻的预成核层。 将初始成核层转变成具有比第一电阻显着小的第二电阻的成核层。 在成核层上形成导电层。 所述导电层，所述成核层，阻挡层和该栅极绝缘层被部分地蚀刻，以形成包括栅极绝缘层图案，阻挡层图案，一个成核层图案和导电层图案的埋入栅极结构。

公开(公告)号：US20100193875A1

公开(公告)日：2010-08-05

申请号：US12759284

申请日：2010-04-13

申请人： Hye-Lan Lee ,  Hag-Ju Cho ,  Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang

发明人： Hye-Lan Lee ,  Hag-Ju Cho ,  Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang

IPC分类号： H01L27/092

CPC分类号： H01L21/823842

摘要： In a semiconductor device with dual gates and a method of manufacturing the same, a dielectric layer and first and second metallic conductive layers are successively formed on the semiconductor substrate having first and second regions. The second metallic conductive layer which is formed on the first metallic conductive layer of the second region is etched to form a metal pattern. The first metallic conductive layer is etched using the metal pattern as an etching mask. A polysilicon layer is formed on the dielectric layer and the metal pattern. The first gate electrode is formed by etching portions of the polysilicon layer, the metal pattern, and the first metallic conductive layer of the first region. The second gate electrode is formed by etching a portion of the polysilicon layer formed directly on the dielectric layer of the second region.

摘要翻译： 在具有双栅极的半导体器件及其制造方法中，在具有第一和第二区域的半导体衬底上依次形成电介质层和第一和第二金属导电层。 形成在第二区域的第一金属导电层上的第二金属导电层被蚀刻以形成金属图案。 使用金属图案作为蚀刻掩模蚀刻第一金属导电层。 在电介质层和金属图案上形成多晶硅层。 第一栅极通过蚀刻第一区域的多晶硅层，金属图案和第一金属导电层的部分而形成。 通过蚀刻直接形成在第二区域的电介质层上的多晶硅层的一部分来形成第二栅电极。

公开(公告)号：US07727841B2

公开(公告)日：2010-06-01

申请号：US11497998

申请日：2006-08-01

申请人： Hye-Lan Lee ,  Hag-Ju Cho ,  Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang

发明人： Hye-Lan Lee ,  Hag-Ju Cho ,  Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842

摘要： In a semiconductor device with dual gates and a method of manufacturing the same, a dielectric layer and first and second metallic conductive layers are successively formed on the semiconductor substrate having first and second regions. The second metallic conductive layer which is formed on the first metallic conductive layer of the second region is etched to form a metal pattern. The first metallic conductive layer is etched using the metal pattern as an etching mask. A polysilicon layer is formed on the dielectric layer and the metal pattern. The first gate electrode is formed by etching portions of the polysilicon layer, the metal pattern, and the first metallic conductive layer of the first region. The second gate electrode is formed by etching a portion of the polysilicon layer formed directly on the dielectric layer of the second region.

摘要翻译： 在具有双栅极的半导体器件及其制造方法中，在具有第一和第二区域的半导体衬底上依次形成电介质层和第一和第二金属导电层。 形成在第二区域的第一金属导电层上的第二金属导电层被蚀刻以形成金属图案。 使用金属图案作为蚀刻掩模蚀刻第一金属导电层。 在电介质层和金属图案上形成多晶硅层。 第一栅极通过蚀刻第一区域的多晶硅层，金属图案和第一金属导电层的部分而形成。 通过蚀刻直接形成在第二区域的电介质层上的多晶硅层的一部分来形成第二栅电极。

公开(公告)号：US20090253256A1

公开(公告)日：2009-10-08

申请号：US12422849

申请日：2009-04-13

申请人： Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Seong-Geon Park ,  Taek-Soo Jeon

发明人： Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Seong-Geon Park ,  Taek-Soo Jeon

IPC分类号： H01L21/8239

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a polysilicon layer contacts a gate insulation film while the other transistor includes a gate structure in which a metal layer contacts a gate insulation film.

摘要翻译： 半导体器件具有彼此不同结构的两个晶体管。 晶体管中的一个是P型，另一个是N型。 一个晶体管包括其中多晶硅层接触栅极绝缘膜的栅极结构，而另一个晶体管包括其中金属层与栅极绝缘膜接触的栅极结构。

公开(公告)号：US20090239348A1

公开(公告)日：2009-09-24

申请号：US12478345

申请日：2009-06-04

申请人： Sun-Ghil Lee ,  Young-Pil Kim ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Young-Eun Lee

发明人： Sun-Ghil Lee ,  Young-Pil Kim ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Young-Eun Lee

IPC分类号： H01L21/336

CPC分类号： C30B29/06 ,  C30B15/00

摘要： A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.

摘要翻译： 公开了一种形成在应变硅层上的半导体器件及其制造方法。 根据本发明，在单晶硅衬底上形成第一硅锗层; 第二硅锗层形成在第一硅锗层上，第二硅锗层的锗浓度在约1重量％至约15重量％的范围内，基于第二硅锗层的总重量 ; 在第二硅锗层上形成应变硅层; 在应变硅层的第一部分处形成隔离层; 在应变硅层上形成栅极结构; 并且源极/漏极区域形成在与栅极结构相邻的应变硅层的第二部分处以形成晶体管。

公开(公告)号：US07553742B2

公开(公告)日：2009-06-30

申请号：US11329158

申请日：2006-01-11

申请人： Yong-Hoon Son ,  Yu-Gyun Shin ,  Jong-Wook Lee

发明人： Yong-Hoon Son ,  Yu-Gyun Shin ,  Jong-Wook Lee

IPC分类号： H01L21/76

CPC分类号： C30B25/04 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639

摘要： A method of forming a thin layer including providing a first single-crystalline silicon layer partially exposed through an opening in an insulation pattern and forming an epitaxial layer on the first single-crystalline silicon layer and forming an amorphous silicon layer on the insulation pattern, the amorphous silicon layer having a first portion adjacent the epitaxial layer and a second portion spaced apart from the first portion, wherein the amorphous silicon layer is formed on the insulation pattern at substantially the same rate at the first portion and at a second portion. The amorphous silicon layer may be formed to a uniform thickness without a thinning defect.

摘要翻译： 一种形成薄层的方法，包括提供通过绝缘图案中的开口局部暴露的第一单晶硅层，并在第一单晶硅层上形成外延层，并在绝缘图案上形成非晶硅层， 非晶硅层，其具有与外延层相邻的第一部分和与第一部分间隔开的第二部分，其中非晶硅层在第一部分和第二部分以基本上相同的速率形成在绝缘图案上。 可以将非晶硅层形成为均匀的厚度而没有变薄的缺陷。

公开(公告)号：US07531881B2

公开(公告)日：2009-05-12

申请号：US11400560

申请日：2006-04-07

申请人： Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Seong-Geon Park ,  Taek-Soo Jeon

发明人： Hye-Lan Lee ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Seong-Geon Park ,  Taek-Soo Jeon

IPC分类号： H01L29/76

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a polysilicon layer contacts a gate insulation film while the other transistor includes a gate structure in which a metal layer contacts a gate insulation film.

摘要翻译： 半导体器件具有彼此不同结构的两个晶体管。 晶体管中的一个是P型，另一个是N型。 一个晶体管包括其中多晶硅层接触栅极绝缘膜的栅极结构，而另一个晶体管包括其中金属层与栅极绝缘膜接触的栅极结构。

公开(公告)号：US07390719B2

公开(公告)日：2008-06-24

申请号：US11497972

申请日：2006-08-01

申请人： Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Hye-Lan Lee ,  Sang-Yong Kim

发明人： Taek-Soo Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hag-Ju Cho ,  Hye-Lan Lee ,  Sang-Yong Kim

IPC分类号： H01L21/8234

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/78

摘要： A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed to have a reduced etching rate. A second metallic conductive layer is formed on the first metallic conductive layer to a second thickness that is greater than the first thickness. A portion of the second metallic conductive layer formed in a second area of the substrate is removed using an etching selectivity. A first gate structure having a first metallic gate including the first and the second metallic conductive layers is formed in a first area of the substrate. A second gate structure having a second metallic gate is formed in the second area. A gate dielectric layer is not exposed to an etching chemical due to the first metallic conductive layer, so its dielectric characteristics are not degraded.

摘要翻译： 具有双栅极的半导体器件形成在具有电介质层的衬底上。 在电介质层上形成第一金属导电层至第一厚度，并且退火以降低蚀刻速率。 在第一金属导电层上形成第二金属导电层至大于第一厚度的第二厚度。 使用蚀刻选择性去除在衬底的第二区域中形成的第二金属导电层的一部分。 具有包括第一和第二金属导电层的第一金属栅极的第一栅极结构形成在衬底的第一区域中。 具有第二金属栅极的第二栅极结构形成在第二区域中。 由于第一金属导电层，栅极电介质层不暴露于蚀刻化学品，因此其介电特性不劣化。

公开(公告)号：US07351622B2

公开(公告)日：2008-04-01

申请号：US11490613

申请日：2006-07-21

申请人： Gyoung-Ho Buh ,  Chang-Woo Ryoo ,  Yu-Gyun Shin ,  Tai-Su Park ,  Jin-Wook Lee

发明人： Gyoung-Ho Buh ,  Chang-Woo Ryoo ,  Yu-Gyun Shin ,  Tai-Su Park ,  Jin-Wook Lee

IPC分类号： H01L21/84 ,  H01L21/8234 ,  H01L21/336 ,  H01L21/00

CPC分类号： H01L29/7851 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/66803

摘要： A method of forming a semiconductor device includes forming a three-dimensional structure formed of a semiconductor on a semiconductor substrate, and isotropically doping the three-dimensional structure by performing a plasma doping process using a first source gas and a second source gas. The first source gas includes n-type or p-type impurity elements, and the second source gas includes a dilution element regardless of the electrical characteristic of a doped region.

摘要翻译： 形成半导体器件的方法包括在半导体衬底上形成由半导体形成的三维结构，并且通过使用第一源气体和第二源气体进行等离子体掺杂工艺，对三维结构进行各向同性地掺杂。 第一源气体包括n型或p型杂质元素，第二源气体包括稀释元件，而与掺杂区域的电特性无关。