公开(公告)号：US07256137B2

公开(公告)日：2007-08-14

申请号：US11052938

申请日：2005-02-07

申请人： Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue ,  Ju-Wang Hsu ,  Ming-Huan Tsai

发明人： Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue ,  Ju-Wang Hsu ,  Ming-Huan Tsai

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76829 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76832

摘要： A method of manufacturing a semiconductor device is provided comprising the steps of: (a) forming a semiconductor element on a substrate, the semiconductor element having at least one nickel silicide contact region, a first etch stop layer formed over the element and an insulating layer formed over the first etch stop layer; (b) forming an opening through the insulating layer over the contact region at least to the first etch stop layer; (c) removing a portion of the first etch stop layer contacting a selected contact region using a process that does not substantially oxidize with the contact region, to form a contact opening to the contact region; and (d) filling the contact opening with conductive material to form a contact.

摘要翻译： 提供一种制造半导体器件的方法，包括以下步骤：（a）在衬底上形成半导体元件，所述半导体元件具有至少一个硅化镍接触区域，形成在元件上的第一蚀刻停止层和绝缘层 形成在第一蚀刻停止层上; （b）至少在所述第一蚀刻停止层上在所述接触区域上形成穿过所述绝缘层的开口; （c）使用不与接触区域基本上氧化的工艺去除与所选择的接触区域接触的第一蚀刻停止层的一部分，以形成到接触区域的接触开口; 和（d）用导电材料填充接触开口以形成接触。

公开(公告)号：US07205234B2

公开(公告)日：2007-04-17

申请号：US10772938

申请日：2004-02-05

申请人： Chii-Ming Wu ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

发明人： Chii-Ming Wu ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC分类号： H01L21/44

CPC分类号： H01L21/28052 ,  H01L21/28518 ,  H01L21/823835 ,  H01L29/665

摘要： A method of optimizing the formation of nickel silicide on regions of a MOSFET structure, has been developed. The method features formation of nickel silicide using an anneal procedure performed at a temperature below which nickel silicide instability and agglomeration occurs. A thin titanium interlayer is first formed on the MOSFET structure prior to nickel deposition, allowing an anneal procedure, performed after nickel deposition, to successfully form nickel silicide at a temperature of about 400° C. To obtain the desired conformality and thickness uniformity the thin titanium interlayer is formed via an atomic layer deposition procedure.

摘要翻译： 已经开发了在MOSFET结构的区域上优化硅化镍的形成的方法。 该方法的特征是使用在低于该温度的镍硅化物不稳定性和聚集发生的温度下进行的退火程序形成硅化镍。 首先在镍沉积之前在MOSFET结构上形成薄的钛中间层，允许在镍沉积之后进行的退火程序在约400℃的温度下成功形成硅化镍。为了获得所需的共形性和厚度均匀性，薄的 通过原子层沉积工艺形成钛夹层。

公开(公告)号：US07183413B2

公开(公告)日：2007-02-27

申请号：US10819646

申请日：2004-04-06

申请人： Chu-Chung Lin ,  Jen-Fuh Liu ,  Chih-Wei Chang ,  Shu-Jen Chen ,  Yibin Xiang ,  Pei-Chin Cheng ,  Jiing-Jyh Jan

发明人： Chu-Chung Lin ,  Jen-Fuh Liu ,  Chih-Wei Chang ,  Shu-Jen Chen ,  Yibin Xiang ,  Pei-Chin Cheng ,  Jiing-Jyh Jan

IPC分类号： C07D215/16 ,  C07D215/38

CPC分类号： C07D401/14 ,  A61K31/4745 ,  A61K31/519 ,  C07D215/42 ,  C07D215/44 ,  C07D215/46 ,  C07D219/12 ,  C07D221/16 ,  C07D401/12 ,  C07D409/14 ,  C07D413/14 ,  C07D417/12 ,  C07D417/14 ,  C07D471/04

摘要： This invention relates to treating inflammatory and immune diseases with certain aminoquinoline compounds that bind to CXCR3 receptors. The aminoquinoline compounds are covered by the formula (I) shown below. Each variable is defined in the specification.

摘要翻译： 本发明涉及用与CXCR3受体结合的某些氨基喹啉化合物治疗炎症和免疫疾病。 氨基喹啉化合物被下面所示的式（I）覆盖。 每个变量在规范中定义。

公开(公告)号：US20070010051A1

公开(公告)日：2007-01-11

申请号：US11174683

申请日：2005-07-05

申请人： Chii-Ming Wu ,  Chih-Wei Chang ,  Pang-Yen Tsai ,  Chih-Chien Chang

发明人： Chii-Ming Wu ,  Chih-Wei Chang ,  Pang-Yen Tsai ,  Chih-Chien Chang

IPC分类号： H01L21/8234 ,  H01L21/4763

CPC分类号： H01L29/665 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7843

摘要： A method of forming MOS devices is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region in the semiconductor substrate, forming an additional layer, preferably by epitaxial growth, on the source/drain region, and siliciding at least a top portion of the additional layer. The additional layer compensates for at least a portion of the semiconductor material lost during manufacturing processes and increases the distance between the source/drain silicide and the substrate. As a result, the leakage current is reduced. A transistor formed using the preferred embodiment preferably includes a silicide over the gate electrode wherein the silicide extends beyond a sidewall boundary of the gate electrode.

摘要翻译： 提供了一种形成MOS器件的方法。 该方法包括提供半导体衬底，在半导体衬底上形成栅极电介质，在栅极电介质上形成栅电极，在半导体衬底中形成源/漏区，在源上形成附加层，优选通过外延生长 /漏极区域，并且至少将附加层的顶部部分硅化。 附加层补偿在制造过程中损失的半导体材料的至少一部分，并且增加源极/漏极硅化物和衬底之间的距离。 结果，泄漏电流降低。 使用优选实施例形成的晶体管优选地包括在栅极上的硅化物，其中硅化物延伸超过栅电极的侧壁边界。

公开(公告)号：US20060246720A1

公开(公告)日：2006-11-02

申请号：US11117152

申请日：2005-04-28

申请人： Chii-Ming Wu ,  Shih-Wei Chou ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

发明人： Chii-Ming Wu ,  Shih-Wei Chou ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/28518

摘要： A semiconductor method of manufacture involving suicides is provided. Embodiments comprise forming a stacked arrangement of layers, the stacked arrangement of layers comprising an additive layer on a substrate, and a metal layer on the additive layer, annealing the stacked arrangement of layers to form a metal silicide layer on the substrate, wherein the metal silicide layer includes an additive from the additive layer. Alternative embodiments include etching the stacked arrangement of layers to remove an unreacted material layer. In an alternative embodiment, the stacked arrangement of layer comprises a metal layer on a substrate, an additive layer on the metal layer, and an optional oxygen barrier layer on the additive layer. An annealing process forms a metal silicide containing an additive. Metal silicides formed according to embodiments are particularly resistant to agglomeration during high temperature processing.

摘要翻译： 提供涉及自杀的半导体制造方法。 实施例包括形成层的堆叠布置，在衬底上包括添加层的层的堆叠排列以及添加层上的金属层，退火层的层叠布置以在衬底上形成金属硅化物层，其中金属 硅化物层包括来自添加剂层的添加剂。 替代实施例包括蚀刻层的堆叠布置以去除未反应的材料层。 在替代实施例中，层的堆叠布置包括在基底上的金属层，金属层上的添加层和在添加剂层上的任选的氧阻隔层。 退火工艺形成含有添加剂的金属硅化物。 根据实施例形成的金属硅化物特别耐高温处理期间的附聚。

公开(公告)号：US20050277237A1

公开(公告)日：2005-12-15

申请号：US10867078

申请日：2004-06-14

申请人： Mei-Yun Wang ,  Chih-Wei Chang

发明人： Mei-Yun Wang ,  Chih-Wei Chang

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49

CPC分类号： H01L29/4933 ,  H01L21/28052

摘要： Deep silicidation of a polysilicon gate electrode following high temperature annealing of a source/drain under the gate may damage the gate oxide. This damage is prevented by forming the gate electrode as two polysilicon layers separated by a chemical oxide. During annealing the chemical oxide prevents the grains of one polysilicon layer from merging with the grains of the other polysilicon layer. Thereafter, silicidation is substantially confined to the top polysilicon layer, the low resistance of which shunts the bottom polysilicon layer through the chemical oxide.

摘要翻译： 在栅极下的源极/漏极的高温退火之后，多晶硅栅极的深硅化可能会损坏栅极氧化物。 通过将栅电极形成为由化学氧化物分离的两个多晶硅层来防止这种损伤。 在退火期间，化学氧化物防止一个多晶硅层的晶粒与另一个多晶硅层的晶粒结合。 此后，硅化物基本上限于顶部多晶硅层，其低电阻通过化学氧化物分流底部多晶硅层。

公开(公告)号：US20050272235A1

公开(公告)日：2005-12-08

申请号：US10859730

申请日：2004-06-03

申请人： Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

发明人： Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/4763 ,  H01L29/49

CPC分类号： H01L21/28097 ,  H01L21/28518 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/785

摘要： A method of forming a silicided gate of a field effect transistor on a substrate having active regions is provided. The method includes the following steps: (a) forming a silicide in at least a first portion of a gate; (b) after step (a), depositing a metal over the active regions and said gate; and (c) annealing to cause the metal to react to form silicide in the active regions, wherein the thickness of said gate silicide is greater than the thickness of said silicide in said active regions.

摘要翻译： 提供了在具有有源区的基板上形成场效应晶体管的硅化物栅的方法。 该方法包括以下步骤：（a）在栅极的至少第一部分中形成硅化物; （b）在步骤（a）之后，在有源区域和所述栅极上沉积金属; 和（c）退火以引起金属反应以在有源区中形成硅化物，其中所述栅极硅化物的厚度大于所述有源区中所述硅化物的厚度。

公开(公告)号：US20050158986A1

公开(公告)日：2005-07-21

申请号：US11052938

申请日：2005-02-07

申请人： Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue ,  Ju-Wang Hsu ,  Ming-Huan Tsai

发明人： Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue ,  Ju-Wang Hsu ,  Ming-Huan Tsai

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L21/20 ,  H01L21/4763

CPC分类号： H01L21/76829 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76832

摘要： A method of manufacturing a semiconductor device is provided comprising the steps of: (a) forming a semiconductor element on a substrate, the semiconductor element having at least one nickel silicide contact region, a first etch stop layer formed over the element and an insulating layer formed over the first etch stop layer; (b) forming an opening through the insulating layer over the contact region at least to the first etch stop layer; (c) removing a portion of the first etch stop layer contacting a selected contact region using a process that does not substantially oxidize with the contact region, to form a contact opening to the contact region; and (d) filling the contact opening with conductive material to form a contact.

摘要翻译： 提供一种制造半导体器件的方法，包括以下步骤：（a）在衬底上形成半导体元件，所述半导体元件具有至少一个硅化镍接触区域，形成在元件上的第一蚀刻停止层和绝缘层 形成在第一蚀刻停止层上; （b）至少在所述第一蚀刻停止层上在所述接触区域上形成穿过所述绝缘层的开口; （c）使用不与接触区域基本上氧化的工艺去除与所选择的接触区域接触的第一蚀刻停止层的一部分，以形成到接触区域的接触开口; 和（d）用导电材料填充接触开口以形成接触。

公开(公告)号：US20050092598A1

公开(公告)日：2005-05-05

申请号：US10702970

申请日：2003-11-05

申请人： Mei-Yun Wang ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Cheng-Tung Lin ,  Shau-Lin Shue

发明人： Mei-Yun Wang ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Cheng-Tung Lin ,  Shau-Lin Shue

IPC分类号： C23C14/16 ,  H01L21/285 ,  C23C16/00 ,  C23C14/32

CPC分类号： H01L21/28518 ,  C23C14/16

摘要： A process for reducing the thermal budget and enhancing stability in the thermal budget of a metal salicide process used in the formation of metal salicides on substrates, thus eliminating or reducing salicide spiking and junction leakage in microelectronic devices fabricated on the substrates. According to a typical embodiment, a substrate is cooled to a sub-processing temperature which is lower than the metal deposition processing temperature and the salicide-forming metal is deposited onto the reduced-temperature substrate.

摘要翻译： 一种用于降低热预算并增强用于在基材上形成金属硅化物的金属硅化物工艺的热预算中的稳定性的方法，从而消除或减少在衬底上制造的微电子器件中的自杀剂尖峰和结漏电。 根据典型的实施方式，将基板冷却至比金属沉积处理温度低的副处理温度，并将形成自杀型化合物的金属沉积在还原温度基板上。

公开(公告)号：US06884669B2

公开(公告)日：2005-04-26

申请号：US10894542

申请日：2004-07-19

申请人： Chih-Wei Chang ,  Mei-Yun Wang

发明人： Chih-Wei Chang ,  Mei-Yun Wang

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L29/66507 ,  H01L21/28114 ,  H01L29/665 ,  H01L29/66545

摘要： Alternate methods of forming low resistance “hatted” polysilicon gate elements are provided that increase the effective area in the polysilicon gate for silicide grain growth during silicide formation. The expanded top portion helps to prevent silicide agglomeration in the silicide regions, thereby maintaining or reducing electrode resistance, improving high-frequency performance, and reducing gate delay in sub micron FET ULSI devices, without increasing the underlying active channel length.

摘要翻译： 提供了形成低电阻“帽”多晶硅栅极元件的替代方法，其增加了硅化物形成期间硅化物晶粒生长的多晶硅栅极中的有效面积。 扩展的顶部部分有助于防止硅化物区域中的硅化物聚集，从而在不增加潜在的有源沟道长度的情况下，保持或降低电极电阻，改善高频性能，并减小亚微米FET ULSI器件中的栅极延迟。