公开(公告)号：US10707846B2

公开(公告)日：2020-07-07

申请号：US15992080

申请日：2018-05-29

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: H03K3/356 ,  H03K3/3562 ,  H01L29/66 ,  H03K3/012

Abstract: Described is an apparatus which comprises: a first p-type Tunneling Field-Effect Transistor (TFET); a first n-type TFET coupled in series with the first p-type TFET; a first node coupled to gate terminals of the first p-type and n-type TFETs; a first clock node coupled to a source terminal of the first TFET, the first clock node is to provide a first clock; and a second clock node coupled to a source terminal of the second TFET, the second clock node is to provide a second clock.

公开(公告)号：US10651182B2

公开(公告)日：2020-05-12

申请号：US16146663

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L27/11514 ,  H01L27/11504 ,  H03K19/20 ,  G11C5/06 ,  G11C11/22 ,  H01L29/51

Abstract: An embodiment includes a three dimensional (3D) memory that includes a NOR logic gate, wherein the NOR logic gate includes a ferroelectric based transistor. Other embodiments are addressed herein.

公开(公告)号：US20200091162A1

公开(公告)日：2020-03-19

申请号：US16132281

申请日：2018-09-14

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L27/11507 ,  H01L27/108 ,  H01L23/522 ,  H01L23/532 ,  G11C11/22

Abstract: Described herein are one access transistor and one ferroelectric capacitor (1T-1FE-CAP) memory cells in diagonal arrangements, as well as corresponding methods and devices. When access transistors of memory cells are implemented as FinFETs, then, in a first diagonal arrangement, memory cells are arranged so that the BLs for the cells are diagonal with respect to the fins of the access transistors of the cells, while the WLs for the cells are perpendicular to the fins. In a second diagonal arrangement, memory cells are arranged so that the fins of the access transistors of the cells are diagonal with respect to the WLs for the cells, while the BLs for the cells are perpendicular to the WLs. Such diagonal arrangements may advantageously allow achieving high layout densities of 1T-1FE-CAP memory cells and may benefit from the re-use of front-end transistor process technology with relatively minor adaptations.

公开(公告)号：US10559349B2

公开(公告)日：2020-02-11

申请号：US16078582

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: G11C11/00 ,  G11C11/412 ,  G11C8/16 ,  G11C11/419 ,  H01L27/11 ,  G11C11/22

Abstract: One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.

公开(公告)号：US10381350B2

公开(公告)日：2019-08-13

申请号：US16151175

申请日：2018-10-03

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US10236345B2

公开(公告)日：2019-03-19

申请号：US15569269

申请日：2015-06-22

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Ian A. Young

IPC: H01L29/267 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/205

Abstract: Fermi filter field effect transistors having a Fermi filter between a source and a source contact, systems incorporating such transistors, and methods for forming them are discussed. Such transistors may include a channel between a source and a drain both having a first polarity and a Fermi filter between the source and a source contact such that the Fermi filter has a second polarity complementary to the first polarity.

公开(公告)号：US20190043549A1

公开(公告)日：2019-02-07

申请号：US16144896

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Kaushik Vaidyanathan ,  Daniel H. Morris ,  Huichu Liu ,  Dileep J. Kurian ,  Uygar E. Avci ,  Tanay Karnik ,  Ian A. Young

IPC: G11C11/22 ,  G11C11/413 ,  G06F1/32

Abstract: Embodiments include apparatuses, methods, and systems associated with save-restore circuitry including metal-ferroelectric-metal (MFM) devices. The save-restore circuitry may be coupled to a bit node and/or bit bar node of a pair of cross-coupled inverters to save the state of the bit node and/or bit bar node when an associated circuit block transitions to a sleep state, and restore the state of the bit node and/or bit bar node when the associated circuit block transitions from the sleep state to an active state. The save-restore circuitry may be used in a flip-flop circuit, a register file circuit, and/or another suitable type of circuit. The save-restore circuitry may include a transmission gate coupled between the bit node (or bit bar node) and an internal node, and an MFM device coupled between the internal node and a plate line. Other embodiments may be described and claimed.

公开(公告)号：US20190036018A1

公开(公告)日：2019-01-31

申请号：US16081001

申请日：2016-03-29

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Ian A. Young ,  Dmitri E. Nikonov ,  Ravi Pillarisetty ,  Uygar E. Avci

IPC: H01L43/10 ,  H01L43/02 ,  H01L43/12 ,  H01F10/32 ,  G11C11/16 ,  G11B5/738

Abstract: Described is an apparatus which comprises: a heat spreading layer; a first transition metal layer adjacent to the heat spreading layer; and a magnetic recording layer adjacent to the first transition metal layer. Described is an apparatus which comprises: a first electrode; a magnetic junction having a free magnet; and one or more layers of Jahn-Teller material adjacent to the first electrode and the free magnet of the magnetic junction.

公开(公告)号：US10121792B2

公开(公告)日：2018-11-06

申请号：US15727918

申请日：2017-10-09

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/108 ,  H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US20170178711A1

公开(公告)日：2017-06-22

申请号：US14975439

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: G11C11/22

CPC classification number: G11C11/223 ,  G11C11/221 ,  G11C11/2297 ,  H03K19/0016 ,  H03K19/18

Abstract: Described is an apparatus which comprises: a first power domain having a first inverter to be powered by a first switchable positive supply and a first switchable negative supply; and a second power domain having a second inverter including p-type and n-type FE-FETs, the second inverter having an input coupled to an output of the first inverter.