公开(公告)号：US09246097B2

公开(公告)日：2016-01-26

申请号：US14644382

申请日：2015-03-11

Applicant: Intermolecular Inc.

Inventor： Yun Wang ,  Imran Hashim

IPC: H01L29/02 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/146 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625

Abstract: Provided are resistive random access memory (ReRAM) cells having diffusion barrier layers formed from various materials, such as beryllium oxide or titanium silicon nitrides. Resistive switching layers used in ReRAM cells often need to have at least one inert interface such that substantially no materials pass through this interface. The other (reactive) interface may be used to introduce and remove defects from the resistive switching layers causing the switching. While some electrode materials, such as platinum and doped polysilicon, may form inert interfaces, these materials are often difficult to integrate. To expand electrode material options, a diffusion barrier layer is disposed between an electrode and a resistive switching layer and forms the inert interface with the resistive switching layer. In some embodiments, tantalum nitride and titanium nitride may be used for electrodes separated by such diffusion barrier layers.

公开(公告)号：US20150325788A1

公开(公告)日：2015-11-12

申请号：US14806263

申请日：2015-07-22

Applicant: Intermolecular Inc.

Inventor： Imran Hashim ,  Tony P. Chiang ,  Vidyut Gopal ,  Yun Wang

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1608 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

Abstract: Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.

Abstract translation: 提供了各自包括电阻式开关层和电流控制元件的非易失性存储器组件。 转向元件可以是与开关层串联连接的晶体管。 由转向元件提供的电阻控制允许使用需要低开关电压和电流的开关层。 包括这种开关层的存储器组件比例如需要高得多的开关电压的闪速存储器更容易嵌入到具有其它低电压组件（例如逻辑和数字信号处理组件）的集成电路芯片中。 在一些实施例中，所提供的非易失性存储器组件在小于约3.0V的开关电压和小于50微安的相应电流下工作。 存储元件可以包括设置在氮化钛电极和掺杂多晶硅电极之间的富含金属的氧化铪。 一个电极可以连接到晶体管的漏极或源极，而另一个电极连接到信号线。

公开(公告)号：US09178151B2

公开(公告)日：2015-11-03

申请号：US14078838

申请日：2013-11-13

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1608 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/065 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1641

Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

Abstract translation: 本发明的实施例一般涉及具有设置在至少一个电极和形成在非易失性存储器件中的可变电阻层之间的界面层结构的电阻式开关非易失性存储器件及其形成方法。 通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。 在电阻式开关非易失性存储器件的一种结构中，界面层结构包括钝化区域，界面耦合区域和/或可变电阻层接口区域，其被配置为调整非易失性存储器件的性能，例如降低形成 器件的开关电流并降低器件的成型电压，并降低从一个成形器件到另一个器件的性能变化。

公开(公告)号：US09054307B2

公开(公告)日：2015-06-09

申请号：US14317155

申请日：2014-06-27

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim ,  Tim Minvielle ,  Dipankar Pramanik ,  Takeshi Yamaguchi

IPC: G11C13/00 ,  G11C7/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1608 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/56 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

Abstract: Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon. Other examples include tantalum and/or titanium containing alloys that may also include a combination of silicon and carbon or a combination of aluminum and nitrogen. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature processing. In some embodiments, the breakdown voltage of a current limiting layer is at least about 8V. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layers while maintaining their performance.

Abstract translation: 提供了诸如电阻随机存取存储器（ReRAM）单元的半导体器件，其包括由过渡金属的合金形成的限流层。 这种合金的一些实例包括还可以包括镍，铝和/或硅的含铬合金。 其它实例包括也可以包括硅和碳的组合或铝和氮的组合的含钽和/或钛的合金。 这些限流层可具有至少约1欧姆 - 厘米的电阻率。 即使当这些层受到强电场和/或高温处理时，也保持该电阻率水平。 在一些实施例中，限流层的击穿电压为至少约8V。 层的高电阻率允许在保持其性能的同时缩小包括这些层的半导体器件的尺寸。

公开(公告)号：US20150155486A1

公开(公告)日：2015-06-04

申请号：US14619434

申请日：2015-02-11

Applicant: Intermolecular, Inc.

Inventor： Ronald J. Kuse ,  Tony P. Chiang ,  Imran Hashim

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/1616 ,  H01L45/1641

Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness.

Abstract translation: 描述了具有改进的开关特性的电阻式开关存储元件，包括具有第一电极和第二电极的存储元件，第一电极和第二电极之间的开关层，包括氧化铪并具有第一厚度，以及耦合层， 所述开关层和所述第二电极，所述耦合层包括包含金属钛并且具有小于所述第一厚度的25％的第二厚度的材料。

公开(公告)号：US20150137315A1

公开(公告)日：2015-05-21

申请号：US14599843

申请日：2015-01-19

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

Inventor： Hanhong Chen ,  David Chi ,  Imran Hashim ,  Mitsuhiro Horikawa ,  Sandra G. Malhotra

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/56 ,  H01L27/108 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/75 ,  H01L28/82

Abstract: A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.

公开(公告)号：US08995172B2

公开(公告)日：2015-03-31

申请号：US14186726

申请日：2014-02-21

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim

IPC: G11C11/00 ,  H01L29/02 ,  H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/1253 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/56 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148 ,  H01L45/1616

Abstract: Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.

Abstract translation: 本发明的实施例通常包括一种形成非易失性存储器件的方法，该非易失性存储器件包含由于添加限定在其中的限流部件而具有改进的器件切换性能和寿命的电阻式开关存储元件。 在一个实施例中，限流部件包括至少一层电阻材料，其被配置为提高所形成的电阻式开关存储元件的开关性能和寿命。 所形成的限流层或电阻层的电性能被配置为在逻辑状态编程步骤（即“设定”和“复位”步骤）期间通过添加固定的串联电阻来降低通过可变电阻层的电流 在形成在非易失性存储器件中的电阻式开关存储元件中。 通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。

公开(公告)号：US20150017780A1

公开(公告)日：2015-01-15

申请号：US14504620

申请日：2014-10-02

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim ,  Dipankar Pramanik

IPC: H01L45/00

CPC classification number: H01L45/16 ,  H01L27/2463 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675

Abstract: A nonvolatile resistive memory element includes one or more novel oxygen isolation structures that protect the resistive switching material of the memory element from oxygen migration. One such oxygen isolation structure comprises an oxygen barrier layer that isolates the resistive switching material from other portions of the resistive memory device during fabrication and/or operation of the memory device. Another such oxygen isolation structure comprises a sacrificial layer that reacts with unwanted oxygen migrating toward the resistive switching material during fabrication and/or operation of the memory device.

Abstract translation: 非易失性电阻存储元件包括一个或多个新颖的氧隔离结构，其保护存储元件的电阻开关材料免于氧迁移。 一个这样的氧隔离结构包括氧阻隔层，其在制造和/或操作存储器件期间将电阻性开关材料与电阻式存储器件的其它部分隔离。 另一种这样的氧隔离结构包括牺牲层，其在存储器件的制造和/或操作期间与向电阻开关材料迁移的不想要的氧化反应。

公开(公告)号：US20150001676A1

公开(公告)日：2015-01-01

申请号：US14491080

申请日：2014-09-19

Applicant: Intermolecular, Inc.

Inventor： Venkat Ananthan ,  Imran Hashim ,  Prashant B. Phatak

IPC: H01L27/24 ,  H01L49/02

CPC classification number: H01L27/2418 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L28/40 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633

Abstract: MIMCAP devices are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP devices can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a low defect dielectric layer, a high defect dielectric layer, sandwiched between two electrodes having different work function values.

Abstract translation: 提供了可适用于存储器件应用的MIMCAP器件，例如用于交叉点存储器阵列的电流选择器装置。 与MIMCAP隧道二极管相比，MIMCAP器件与肖特基二极管相比可以具有更低的热量预算，并且可控制的较低势垒高度和较低的串联电阻。 MIMCAP二极管可以包括夹在具有不同功函数值的两个电极之间的低缺陷电介质层，高缺陷电介质层。

公开(公告)号：US20140361235A1

公开(公告)日：2014-12-11

申请号：US14469282

申请日：2014-08-26

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim ,  Tim Minvielle ,  Takeshi Yamaguchi

IPC: H01L45/00

CPC classification number: H01L45/145 ,  B82Y10/00 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608

Abstract: A nonvolatile resistive memory element has a novel variable resistance layer that includes a metal nitride, a metal oxide-nitride, a two-metal oxide-nitride, or a multilayer stack thereof. One method of forming the novel variable resistance layer comprises an interlayer deposition procedure, in which metal oxide layers are interspersed with metal nitride layers and then converted into a substantially homogeneous layer by an anneal process. Another method of forming the novel variable resistance layer comprises an intralayer deposition procedure, in which various ALD processes are sequentially interleaved to form a metal oxide-nitride layer. Alternatively, a metal oxide is deposited, nitridized, and annealed to form the variable resistance layer or a metal nitride is deposited, oxidized, and annealed to form the variable resistance layer.

Abstract translation: 非易失性电阻存储元件具有新颖的可变电阻层，其包括金属氮化物，金属氧化物氮化物，二金属氧化物氮化物或其多层叠层。 形成新颖的可变电阻层的一种方法包括层间沉积程序，其中金属氧化物层散布有金属氮化物层，然后通过退火工艺转变成基本均匀的层。 形成新型可变电阻层的另一种方法包括层间沉积程序，其中各种ALD工艺顺序交错以形成金属氧化物 - 氮化物层。 或者，金属氧化物被沉积，氮化和退火以形成可变电阻层，或者金属氮化物被沉积，氧化和退火以形成可变电阻层。