公开(公告)号：US20150044787A1

公开(公告)日：2015-02-12

申请号：US14524637

申请日：2014-10-27

Applicant: International Business Machines Corporation

Inventor： James V. Crain, JR. ,  Mark C.H. Lamorey ,  Christopher D. Muzzy ,  Thomas M. Shaw ,  David B. Stone

IPC: H01L21/66 ,  G01R31/26 ,  H01L23/00

CPC classification number: H01L22/34 ,  G01R31/2601 ,  G01R31/2607 ,  H01L23/522 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/13111 ,  H01L2224/14131 ,  H01L2224/14515 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/14

Abstract: A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.

Abstract translation: 公开了一种测试集成电路（IC）芯片和相关测试结构的方法。 测试结构包括靠近至少一个焊料凸块焊盘的监视器链，监视器链包括至少一个金属通孔堆叠，每个金属通孔堆叠从IC芯片中的下金属层延伸到IC芯片中的上金属层 使得监视器链形成靠近至少一个焊料凸块焊盘的连续电路，并且其中每个金属通孔叠层基本位于焊料凸块的下方。 用于检测安全有效模量边界的测试方法包括对包含连接到半导体封装的测试结构的IC芯片执行应力测试。

公开(公告)号：US08933540B2

公开(公告)日：2015-01-13

申请号：US13780033

申请日：2013-02-28

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Michael J. Hauser ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/34 ,  H01L25/00

CPC classification number: H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589

Abstract: A three dimensional integrated circuit (3D-IC) structure, method of manufacturing the same and design structure thereof are provided. The 3D-IC structure includes two chips having a dielectric layer, through substrate vias (TSVs) and pads formed on the dielectric layer. The dielectric layer is formed on a bottom surface of each chip. Pads are electrically connected to the corresponding TSVs. The chips are disposed vertically adjacent to each other. The bottom surface of a second chip faces the bottom surface of a first chip. The pads of the first chip are electrically connected to the pads of the second chip through a plurality of conductive bumps. The 3D-IC structure further includes a thermal via structure vertically disposed between the first chip and the second chip and laterally disposed between the corresponding conductive bumps. The thermal via structure has an upper portion and a lower portion.

Abstract translation: 提供三维集成电路（3D-IC）结构，其制造方法及其设计结构。 3D-IC结构包括具有介电层的两个芯片，通过衬底通孔（TSV）和形成在电介质层上的焊盘。 电介质层形成在每个芯片的底表面上。 垫片电连接到相应的TSV。 芯片垂直相邻配置。 第二芯片的底表面面向第一芯片的底表面。 第一芯片的焊盘通过多个导电凸块电连接到第二芯片的焊盘。 3D-IC结构还包括垂直设置在第一芯片和第二芯片之间并横向设置在相应的导电凸块之间的热通孔结构。 热通孔结构具有上部和下部。

公开(公告)号：US08927334B2

公开(公告)日：2015-01-06

申请号：US13626032

申请日：2012-09-25

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Nathalie Normand ,  David L. Questad ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L23/3164 ,  H01L23/291 ,  H01L23/293 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11001 ,  H01L2224/11011 ,  H01L2224/1131 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81007 ,  H01L2224/81191 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/00

Abstract: Structures and methods for forming good electrical connections between an integrated circuit (IC) chip and a chip carrier of a flip chip package include forming one of: a tensile layer on a front side of the IC chip, which faces a tops surface of the chip carrier, and a compressive layer on the backside of the IC chip. Addition of one of: a tensile layer to the front side of the IC chip and a compressive layer the backside of the IC chip, may reduce or modulate warpage of the IC chip and enhance wetting of opposing solder surfaces of solder bumps on the IC chip and solder formed on flip chip (FC) attaches of a chip carrier during making of the flip chip package.

Abstract translation: 用于在集成电路（IC）芯片和倒装芯片封装的芯片载体之间形成良好电连接的结构和方法包括形成以下之一：IC芯片正面上的面向芯片顶表面的拉伸层 载体和IC芯片背面的压缩层。 添加IC芯片的前侧的拉伸层和IC芯片的背面的压缩层可以减少或调制IC芯片的翘曲并增强IC芯片上的焊料凸块的相对焊接表面的润湿 并且在制造倒装芯片封装期间在芯片载体的倒装芯片（FC）上形成焊料。

公开(公告)号：US20150001683A1

公开(公告)日：2015-01-01

申请号：US13928676

申请日：2013-06-27

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Charles F. Musante ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L21/78 ,  H01L29/41 ,  H01L21/283 ,  H01L29/06

CPC classification number: H01L21/78 ,  H01L21/283

Abstract: A method including forming a plurality of dicing channels in a front side of a wafer; the plurality of dicing channels including a depth at least greater than a desired final thickness of the wafer, filling the plurality of dicing channels with a fill material and removing a portion of the wafer from a back side of the wafer until the desired final thickness is achieved, where a portion of the fill material within the plurality of dicing channel is exposed. The method further including depositing a metal layer on the back side of the wafer; removing the fill material from within the plurality of dicing channels to expose the metal layer at a bottom of the plurality of dicing channels, and removing a portion of the metal layer located at the bottom of the plurality of dicing channels.

Abstract translation: 一种包括在晶片的前侧形成多个切割通道的方法; 多个切割通道包括至少大于晶片的期望最终厚度的深度，用填充材料填充多个切割通道，并从晶片的背面去除晶片的一部分，直到期望的最终厚度为 其中多个切割通道内的填充材料的一部分被暴露。 该方法还包括在晶片的背面沉积金属层; 从所述多个切割通道内移除所述填充材料以暴露所述多个切割通道的底部处的所述金属层，以及去除位于所述多个切割通道的底部的所述金属层的一部分。