公开(公告)号：US10747850B2

公开(公告)日：2020-08-18

申请号：US15083960

申请日：2016-03-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Maryam Ashoori ,  Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Leigh Anne H. Clevenger ,  Jonathan H. Connell, II ,  Nalini K. Ratha ,  Michael Rizzolo

IPC: G06F19/00 ,  G16H10/60

Abstract: Embodiments include method, systems and computer program products for providing medication-related feedback. Aspects include receiving medication information for a patient. Aspects also include receiving a biological, behavioral, or environmental output from a sensor. Aspects also include determining, based upon the biological, behavioral, or environmental output and the medication information for the patient, whether a medication dose is needed. Aspects also include, based on a determination that the medication dose is needed, generating an alert.

公开(公告)号：US10720567B2

公开(公告)日：2020-07-21

申请号：US15972423

申请日：2018-05-07

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Nicholas A. Lanzillo ,  Michael Rizzolo ,  Theodorus E. Standaert

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08

Abstract: Techniques for preventing switching of spins in a magnetic tunnel junction by stray magnetic fields using a thin film magnetic shield are provided. In one aspect, a method of forming a magnetic tunnel junction includes: forming a stack on a substrate, having a first magnetic layer, a tunnel barrier, and a second magnetic layer; etching the stack to partially pattern the magnetic tunnel junction in the stack, wherein the etching includes patterning the magnetic tunnel junction through the second magnetic layer, the tunnel barrier, and partway through the first magnetic layer; depositing a first spacer and a magnetic shield film onto the partially patterned magnetic tunnel junction; etching back the magnetic shield film and first spacer; complete etching of the magnetic tunnel junction through the first magnetic layer to form a fully patterned magnetic tunnel junction; and depositing a second spacer onto the fully patterned magnetic tunnel junction.

公开(公告)号：US10692925B2

公开(公告)日：2020-06-23

申请号：US16159220

申请日：2018-10-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael Rizzolo ,  Theodorus E. Standaert ,  Isabel Cristina Chu ,  Chih-Chao Yang ,  Son Nguyen

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A method for fabricating a semiconductor device includes forming one or more encapsulation spacers each about respective ones of one more memory pillar elements to have a geometry, including forming each encapsulation spacer to have a footing of at least about twice a critical dimension of its corresponding pillar, and depositing dielectric material on the one or more memory pillar elements and the one or more encapsulation spacers to form an interlayer dielectric free of voids based on the geometry.

公开(公告)号：US20200176263A1

公开(公告)日：2020-06-04

申请号：US16204336

申请日：2018-11-29

Applicant: International Business Machines Corporation

Inventor： Mona A. Ebrish ,  Michael Rizzolo ,  Son Nguyen ,  Raghuveer R. Patlolla ,  Donald F. Canaperi

IPC: H01L21/3105 ,  H01L21/311 ,  H01L27/22 ,  H01L29/78

Abstract: A semiconductor device and method of formation thereof. The semiconductor device includes a portion of a first material that abuts a portion of a second material and surrounds at least a portion of a semiconductor component. The first material has a first composition and a first index of refraction and is of a same type of material as the second material. The second material has a second composition and a second index of refraction. An opening in the first material exposes a portion of the semiconductor component.

公开(公告)号：US10672984B2

公开(公告)日：2020-06-02

申请号：US16414339

申请日：2019-05-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Michael Rizzolo ,  Lawrence A. Clevenger ,  Shyng-Tsong Chen

IPC: H01L45/00 ,  G06N3/04 ,  H01L27/24

Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a RRAM stack including a bottom electrode, a top electrode, and a bi-layer hardmask, forming a low-k dielectric layer over the RRAM stack, removing a first layer of the bi-layer hardmask during a via opening, and removing a second layer of the bilayer hardmask concurrently with a plurality of sacrificial layers formed over the low-k dielectric layer.

公开(公告)号：US20200091079A1

公开(公告)日：2020-03-19

申请号：US16690925

申请日：2019-11-21

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Nicholas A. Lanzillo ,  Takeshi Nogami ,  Christopher J. Penny ,  Michael Rizzolo

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric.

公开(公告)号：US20200090988A1

公开(公告)日：2020-03-19

申请号：US16131354

申请日：2018-09-14

Applicant: International Business Machines Corporation

Inventor： Cornelius B. Peethala ,  Michael Rizzolo ,  Oscar Van Der Straten ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/532

Abstract: According to embodiments of the present invention, a semiconductor wafer includes a substrate and an interlayer dielectric located on the substrate. The interlayer dielectric includes an interconnect. A barrier layer is located in between the interconnect and the interlayer dielectric. A semi-liner layer is located in between the interconnect and the barrier layer. The interlayer dielectric, the interconnect, and barrier layer form a substantially planar surface opposite the substrate. The interconnect has an interconnect height from a base to the substantially planar surface and a semi-liner height of the semi-liner layer is less than the interconnect height such that liner layer does not extend to the planar surface.

公开(公告)号：US20200081761A1

公开(公告)日：2020-03-12

申请号：US16683791

申请日：2019-11-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Leigh Anne H. Clevenger ,  Christopher J. Penny ,  Michael Rizzolo ,  Aldis G. Sipolins

IPC: G06F11/07 ,  G06T19/20 ,  H04N1/00

Abstract: Methods and systems for printing accurate three-dimensional structures include printing an original three-dimensional structure according to an original three-dimensional model. The original three-dimensional model is adjusted to reduce measured differences between the printed three-dimensional structure and the original three-dimensional model, by adding material to the original three-dimensional model in proportion to an amount of thermal contraction in a region. An adjusted three-dimensional structure is printed according to the adjusted three-dimensional model.

公开(公告)号：US10586767B2

公开(公告)日：2020-03-10

申请号：US16039570

申请日：2018-07-19

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Cornelius Brown Peethala ,  Michael Rizzolo ,  Koichi Motoyama ,  Gen Tsutsui ,  Ruqiang Bao ,  Gangadhara Raja Muthinti ,  Lawrence A. Clevenger

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/48 ,  H01L21/768 ,  H01L21/306

Abstract: A method for fabricating semiconductor wafers comprises creating a semiconductor wafer having a plurality of wide copper wires and a plurality of narrow copper wires embedded in a dielectric insulator. The width of each wide copper wire is greater than a cutoff value and each narrow copper is less than the cutoff value. An optical pass through layer is deposited over a top surface of the wafer and a photo-resist layer is deposited over the optical pass through layer. The wafer is exposed to a light source to selectively remove photo-resist, forming a self-aligned pattern where photo-resist only remains in areas above wide copper wires. The self-aligned pattern is transferred to the optical pass through layer and the remaining photo-resist is removed. The wafer is chemically etched to remove the narrow copper wires, defining narrow gaps in the dielectric insulator. The wafer is metallized with non-copper metal, forming narrow non-copper metal wires.

公开(公告)号：US10559498B2

公开(公告)日：2020-02-11

申请号：US16410475

申请日：2019-05-13

Applicant: International Business Machines Corporation

Inventor： Benjamin David Briggs ,  Lawrence A. Clevenger ,  Bartlet H. Deprospo ,  Michael Rizzolo

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/67 ,  H01L21/66 ,  B23K26/082 ,  B23K26/00 ,  B23K26/03 ,  B23K26/70 ,  B23K26/062 ,  B23K26/352 ,  H01L23/532

Abstract: A method (and structure) includes performing an initial partial anneal of a metal interconnect overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer. Orientation of an early recrystallizing grain at a specific location on a top surface of the metal overburden layer is determined, as implemented and controlled by a processor on a computer. A determination is made whether the orientation of the early recrystallizing grain is desirable or undesirable.