公开(公告)号：US20240297167A1

公开(公告)日：2024-09-05

申请号：US18176551

申请日：2023-03-01

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Brent A. Anderson ,  Albert M. Chu ,  Lawrence A. Clevenger ,  Nicholas Anthony Lanzillo ,  Reinaldo Vega ,  David Wolpert

IPC: H01L27/02 ,  H01L21/768 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L21/76877 ,  H01L27/11807 ,  H01L2027/11831

Abstract: A semiconductor structure includes a first plurality of backside power rail interconnects located within a first cell height region of a substrate. A second plurality of backside power rail interconnects are located within a second cell height region of the substrate. A first isolation region is located between the first cell height region of the substrate and the second cell height region of the substrate. The first isolation region electrically separates the first cell height region and the second cell height region. A second isolation region is located between adjacent power rail interconnects of the first plurality of backside power rail interconnects and between adjacent power rail interconnects of the second plurality of backside power rail interconnects. The second isolation region electrically separates the adjacent power rail interconnects.

公开(公告)号：US12057387B2

公开(公告)日：2024-08-06

申请号：US17110381

申请日：2020-12-03

Applicant: International Business Machines Corporation

Inventor： Reinaldo Vega ,  David Wolpert ,  Takashi Ando ,  Praneet Adusumilli ,  Cheng Chi

IPC: H01L23/522 ,  H01L23/528 ,  H01L29/423 ,  H01L29/66 ,  H01L29/94 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L23/5286 ,  H01L28/55 ,  H01L29/4236 ,  H01L29/66181 ,  H01L29/945

Abstract: An approach to forming a semiconductor device where the semiconductor device includes a first power rail with one or more vertically stacked contact vias connecting to the first power rail to a portion of a first de-coupling capacitor. The semiconductor device includes the first de-coupling capacitor in a first portion of a semiconductor substrate in a first gate cut trench.

公开(公告)号：US20240234306A9

公开(公告)日：2024-07-11

申请号：US17969773

申请日：2022-10-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Reinaldo Vega ,  Nicholas Anthony Lanzillo ,  Takashi Ando ,  David Wolpert ,  Albert M. Chu ,  Albert M. Young

IPC: H01L23/528 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/32139 ,  H01L21/76892 ,  H01L23/5226

Abstract: A semiconductor structure is presented including a first level of interconnect wiring separated into a first interconnect wiring segment and a second interconnect wiring segment, the first interconnect wiring segment defining a first line segment and the second interconnect wiring segment defining a second line segment and a second level interconnect wiring positioned orthogonally to the first level of interconnect wiring. A distalmost end of the first line segment and a distalmost end of the second line segment are separated by a spacing less than or equal to a spacing of the second level interconnect wiring defining a zero track skip.

公开(公告)号：US12015069B2

公开(公告)日：2024-06-18

申请号：US16745049

申请日：2020-01-16

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Michael A. Guillorn ,  Terence Hook ,  Robert R. Robison ,  Reinaldo Vega ,  Tenko Yamashita

IPC: H01L29/423 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

公开(公告)号：US11973141B2

公开(公告)日：2024-04-30

申请号：US17397068

申请日：2021-08-09

Applicant: International Business Machines Corporation

Inventor： Jingyun Zhang ,  Reinaldo Vega ,  Miaomiao Wang ,  Takashi Ando

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/78391 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/6684 ,  H01L29/78696

Abstract: A nanosheet semiconductor device includes a first ferroelectric region between a channel nanosheet stack and a gate contact. The channel nanosheet stack includes a plurality of channel nanosheets each connected to a source and connected to a drain and a gate surrounding the plurality of channel nanosheets and connected to the source and connected to the drain. The nanosheet semiconductor device may further include a second ferroelectric region upon a sidewall of the channel nanosheet stack. Sidewalls of the first ferroelectric region may be substantially coplanar with or inset from underlying sidewalls of the channel nanosheet stack.

公开(公告)号：US20240096794A1

公开(公告)日：2024-03-21

申请号：US17945498

申请日：2022-09-15

Applicant: International Business Machines Corporation

Inventor： Nicholas Anthony Lanzillo ,  Brent A. Anderson ,  Lawrence A. Clevenger ,  Ruilong Xie ,  Albert M. Chu ,  Reinaldo Vega

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/5283 ,  H01L21/76807 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5228 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device includes: a first via level forming a bottom jumper configured to provide an output; a first set of two or more first metallization tracks overlying the first via level; a second via level forming a first top jumper overlying the first set of two or more first metallization tracks; and a second metallization track overlying the second via level.

公开(公告)号：US11894442B2

公开(公告)日：2024-02-06

申请号：US17358275

申请日：2021-06-25

Applicant: International Business Machines Corporation

Inventor： Jingyun Zhang ,  Ruilong Xie ,  Reinaldo Vega ,  Kangguo Cheng ,  Lan Yu

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/6653 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696 ,  H01L29/0665 ,  H01L29/42392

Abstract: Embodiments disclosed herein include a nanosheet transistor for reducing parasitic capacitance. The nanosheet transistor may include a spacer region between a high-k metal gate and an epitaxial layer. The spacer region may include a first nanosheet stack with a first nanosheet and a second nanosheet. The spacer region may include an inner spacer region between the first nanosheet and the second nanosheet, and a side subway region located along an edge of the first nanosheet, the inner spacer region, and the second nanosheet.

公开(公告)号：US20230093462A1

公开(公告)日：2023-03-23

申请号：US17482874

申请日：2021-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Reinaldo Vega ,  Takashi Ando ,  Cheng Chi ,  Praneet Adusumilli

IPC: H01L23/522 ,  H01L23/528

Abstract: A field effect device is provided. The field effect device includes an active gate structure, a gate contact within the active gate structure, wherein the gate contact is the same height as the active gate structure, and a gate cut dielectric on opposite sides of the gate contact and active gate structure.

公开(公告)号：US11481611B2

公开(公告)日：2022-10-25

申请号：US16178627

申请日：2018-11-02

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Reinaldo Vega ,  Hari Mallela

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: Provided are embodiments of a multi-task learning system with hardware acceleration that includes a resistive random access memory crossbar array. Aspects of the invention includes an input layer that has one or more input layer nodes for performing one or more tasks of the multi-task learning system, a hidden layer that has one or more hidden layer nodes, and a shared hidden layer that has one or more shared hidden layer nodes which represent a parameter, wherein the shared hidden layer nodes are coupled to each of the one or more hidden layer nodes of the hidden layer.

公开(公告)号：US11456416B2

公开(公告)日：2022-09-27

申请号：US16952234

申请日：2020-11-19

Applicant: International Business Machines Corporation

Inventor： Praneet Adusumilli ,  Takashi Ando ,  Reinaldo Vega ,  Cheng Chi

IPC: H01L45/00 ,  H01L27/24 ,  G06N3/08

Abstract: A resistive random access memory (ReRAM) device is provided. The ReRAM device includes a stack structure including a first electrode, a metal oxide layer in contact with the first electrode, and a second electrode in contact with the metal oxide layer. A portion of the stack structure is modified by ion implantation, and the modified portion of the stack structure is offset from edges of the stack structure.