公开(公告)号：US11921652B2

公开(公告)日：2024-03-05

申请号：US17705439

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Kenneth P. Foust ,  Amit Kumar Srivastava ,  George Vergis

IPC: G06F13/42 ,  G06F12/06 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1673 ,  G06F12/0623 ,  G06F12/063 ,  G06F13/4027 ,  G06F13/4282

Abstract: In one embodiment, a host controller includes: a first input/output (I/O) buffer to couple to a first communication line of an interconnect; a second I/O buffer to couple to a second communication line of the interconnect; and a device group selection circuit to dynamically cause the first communication line to communicate a clock signal to a first device group including one or more first devices to couple to the interconnect and dynamically cause the second communication line to communicate a data signal to the first device group when a communication is to be addressed to at least one of the one or more first devices of the first device group, such that the communication is transparent to at least another device group to couple to the interconnect. Other embodiments are described and claimed.

公开(公告)号：US11567895B2

公开(公告)日：2023-01-31

申请号：US17337497

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Kenneth P. Foust ,  Amit Kumar Srivastava ,  Nobuyuki Suzuki

IPC: G06F13/38 ,  G06F13/42 ,  G06F13/364 ,  G06F13/24

Abstract: In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed.

公开(公告)号：US20220302918A1

公开(公告)日：2022-09-22

申请号：US17204792

申请日：2021-03-17

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Noam Familia

IPC: H03L7/099 ,  H03L7/093 ,  G06F1/10

Abstract: A digital phase spacing detector with programmable delay lines is described. Each programmable delay line receives a clock. The output of the programmable delay lines is compared by a logic and then passed through a glitch detector. Each of the clocks pass through the programmable delay lines that are tuned to a point where the clock edges at the output of the delay lines are aligned and glitches start appearing at the output of the logic. A calibration scheme uses replica cells (replica of VCO cells) in the measurement path. The calibration scheme calculates the average of clock phase differences through a digital control replica buffer, and this average clock phase difference is applied to the VCO delay stage cells. The PLL is then allowed to relock with the calibrated VCO delay stage cells. This process can be repeated several times to reduce the phase errors between the clock phases.

公开(公告)号：US11334511B2

公开(公告)日：2022-05-17

申请号：US16655511

申请日：2019-10-17

Applicant: Intel Corporation

Inventor： Rajesh Bhaskar ,  Enrico Carrieri ,  Kenneth Foust ,  Janusz Jurski ,  Myron Loewen ,  Matthew A. Schnoor ,  Amit Kumar Srivastava ,  George Vergis

IPC: G06F1/10 ,  H04L67/104 ,  G06F13/40 ,  H04L12/40 ,  H04L12/18 ,  H04L29/06

Abstract: In one embodiment, an apparatus includes: a peer-to-peer (P2P) control circuit to issue a P2P communication request to a bus master of a multi-drop interconnect to request authorization to send a P2P transaction to at least one slave device coupled to the multi-drop interconnect; a transmitter to transmit the P2P transaction to the at least one slave device when the bus master grants the authorization for the P2P transaction; and another transmitter to output the clock signal to the multi-drop interconnect during the P2P transaction. Other embodiments are described and claimed.

公开(公告)号：US11314668B2

公开(公告)日：2022-04-26

申请号：US15898909

申请日：2018-02-19

Applicant: Intel Corporation

Inventor： Kenneth P. Foust ,  Amit Kumar Srivastava ,  George Vergis

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/06 ,  G06F13/42

Abstract: In one embodiment, a host controller includes: a first input/output (I/O) buffer to couple to a first communication line of an interconnect; a second I/O buffer to couple to a second communication line of the interconnect; and a device group selection circuit to dynamically cause the first communication line to communicate a clock signal to a first device group including one or more first devices to couple to the interconnect and dynamically cause the second communication line to communicate a data signal to the first device group when a communication is to be addressed to at least one of the one or more first devices of the first device group, such that the communication is transparent to at least another device group to couple to the interconnect. Other embodiments are described and claimed.

公开(公告)号：US20210294772A1

公开(公告)日：2021-09-23

申请号：US17340315

申请日：2021-06-07

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Divya Gupta ,  Michael Karas ,  James Mitchell ,  Malay Trivedi ,  Chung-Chi Wang

IPC: G06F13/42 ,  G06F15/78 ,  G06F9/445 ,  G06F13/40 ,  G06F9/4401

Abstract: In one embodiment, an apparatus includes: a plurality of cores to execute instructions; a firmware agent to execute a first firmware; a Peripheral Component Interconnect Express (PCIe) interface to communicate with a device via a PCIe link; and a boot agent coupled to the PCIe interface to download the PCIe firmware from a non-volatile memory and provide the PCIe firmware to the PCIe interface. The PCIe interface may receive a PCIe firmware for the PCIe interface before the firmware agent is to receive the first firmware. Other embodiments are described and claimed.

公开(公告)号：US20210286754A1

公开(公告)日：2021-09-16

申请号：US17337497

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Kenneth P. Foust ,  Amit Kumar Srivastava ,  Nobuyuki Suzuki

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/24

Abstract: In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed.

公开(公告)号：US20210003629A1

公开(公告)日：2021-01-07

申请号：US17031107

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Asad Azam ,  Amit Kumar Srivastava ,  Enrico Carrieri ,  Rajesh Bhaskar

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/3185 ,  G11C29/32 ,  G11C29/46 ,  G11C29/36 ,  G11C29/08

Abstract: An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor to be configured as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a bock to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed IO interface in response to the functional safety system entering an infield test mode.

公开(公告)号：US10853289B2

公开(公告)日：2020-12-01

申请号：US16221962

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Asad Azam ,  Rajesh Bhaskar ,  Mikal Hunsaker ,  Enrico D. Carrieri

IPC: G06F13/36 ,  G06F13/364 ,  H04L12/801 ,  H04L12/835 ,  G06F13/24 ,  G06F13/16 ,  G06F13/42 ,  H04L5/16

Abstract: In one embodiment, a host controller includes: a first credit tracker comprising at least one credit counter to maintain credit information for a first device; and a first credit handler to send a command code having a first predetermined value to indicate a credit request to request credit information from the first device, where the first credit tracker is to update the at least one credit counter based on receipt of an in-band interrupt from the first device having the credit information. Other embodiments are described and claimed.

公开(公告)号：US10745023B2

公开(公告)日：2020-08-18

申请号：US16021911

申请日：2018-06-28

Applicant: INTEL CORPORATION

Inventor： Amit Kumar Srivastava ,  Asad Azam ,  Jagannadha Rapeta

IPC: B60W50/02 ,  H03K3/037 ,  H03K5/24 ,  G01R19/165 ,  G01R19/12 ,  B60W50/00 ,  B60R16/03

Abstract: A voltage monitoring framework is proposed to predict, report, and correct actions for performance impacting voltage droop due to power supplies in a system-on-a-chip. Both the amplitude and duration of the voltage droop are monitored. By predicting serious voltage droops early, power supplies cross check against each other to avoid catastrophic error, thus ensuring that integrated circuits making up the system-on-a-chip will maintain functional reliability.