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    BI-AXIAL TENSILE STRAINED GE CHANNEL FOR CMOS
    81.
    发明申请
    BI-AXIAL TENSILE STRAINED GE CHANNEL FOR CMOS 有权
    用于CMOS的双向拉伸应变通道

    公开(公告)号：US20160293601A1

    公开(公告)日：2016-10-06

    申请号：US15037618

    申请日：2013-12-27

    Applicant: INTEL CORPORATION

    Inventor： Prashant MAJHI ,  Niloy MUKHERJEE ,  Ravi PILLARISETTY ,  Willy RACHMADY ,  Robert S. CHAU

    IPC: H01L27/092 ,  H01L29/165 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8238

    CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/78669 ,  H01L29/78684

    Abstract: An apparatus comprising a complimentary metal oxide semiconductor (CMOS) inverter including an n-channel metal oxide semiconductor field effect transistor (MOSFET); and a p-channel MOSFET, wherein a material of a channel in the n-channel MOSFET and a material of a channel in the p-channel MOSFET is subject to a bi-axial tensile strain. A method including forming an n-channel metal oxide semiconductor field effect transistor (MOSFET); forming a p-channel MOSFET; and connecting the gate electrodes and the drain regions of the n-channel MOSFET and the p-channel MOSFET, wherein a material of the channel in the n-channel MOSFET and a material of the channel in the p-channel MOSFET is subject to a bi-axial tensile strain.

    Abstract translation: 一种包括具有n沟道金属氧化物半导体场效应晶体管（MOSFET）的互补金属氧化物半导体（CMOS）反相器的装置; 以及p沟道MOSFET，其中n沟道MOSFET中的沟道材料和p沟道MOSFET中的沟道的材料经受双轴向拉伸应变。 一种包括形成n沟道金属氧化物半导体场效应晶体管（MOSFET）的方法; 形成p沟道MOSFET; 以及连接n沟道MOSFET和p沟道MOSFET的栅电极和漏极区，其中n沟道MOSFET中的沟道的材料和p沟道MOSFET中的沟道的材料受到 双向拉伸应变。

    BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES
    82.
    发明申请
    BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20240371700A1

    公开(公告)日：2024-11-07

    申请号：US18774351

    申请日：2024-07-16

    Applicant: Intel Corporation

    Inventor： Aaron D. LILAK ,  Ehren MANNEBACH ,  Anh PHAN ,  Richard E. SCHENKER ,  Stephanie A. BOJARSKI ,  Willy RACHMADY ,  Patrick R. MORROW ,  Jeffrey D. BIELEFELD ,  Gilbert DEWEY ,  Hui Jae YOO

    IPC: H01L21/8234 ,  H01L23/48 ,  H01L23/532 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

    Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

    CONDENSED SOURCE OR DRAIN STRUCTURES WITH HIGH GERMANIUM CONTENT
    88.
    发明申请
    CONDENSED SOURCE OR DRAIN STRUCTURES WITH HIGH GERMANIUM CONTENT 有权

    公开(公告)号：US20220199773A1

    公开(公告)日：2022-06-23

    申请号：US17129860

    申请日：2020-12-21

    Applicant: Intel Corporation

    Inventor： Willy RACHMADY ,  Jack T. KAVALIEROS ,  Siddharth CHOUKSEY ,  Ashish AGRAWAL

    IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

    Abstract: Integrated circuit structures having condensed source or drain structures with high germanium content are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. Each of the first and second epitaxial source or drain structures includes silicon and germanium, with an atomic concentration of germanium greater at a core of the epitaxial source or drain structure than at a periphery of the epitaxial source or drain structure.

    ISOLATION WALLS FOR VERTICALLY STACKED TRANSISTOR STRUCTURES
    90.
    发明申请
    ISOLATION WALLS FOR VERTICALLY STACKED TRANSISTOR STRUCTURES 有权

    公开(公告)号：US20220115372A1

    公开(公告)日：2022-04-14

    申请号：US17555296

    申请日：2021-12-17

    Applicant: Intel Corporation

    Inventor： Aaron LILAK ,  Patrick MORROW ,  Gilbert DEWEY ,  Willy RACHMADY ,  Rishabh MEHANDRU

    IPC: H01L27/06 ,  H01L29/78 ,  H01L29/06 ,  H01L27/02 ,  H01L23/522 ,  H01L21/8234 ,  H01L21/822

    Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a lower device layer that includes a first transistor structure, an upper device layer above the lower device layer including a second transistor structure, and an isolation wall that extends between the upper device layer and the lower device layer. The isolation wall may be in contact with an edge of a first gate structure of the first transistor structure and an edge of a second gate structure of the second transistor structure, and may have a first width to the edge of the first gate structure at the lower device layer, and a second width to the edge of the second gate structure at the upper device layer. The first width may be different from the second width. Other embodiments may be described and/or claimed.

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