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112 条记录 (耗时 0.034 秒)

    Flexible FPGA input/output architecture
    81.
    发明授权
    Flexible FPGA input/output architecture 失效
    灵活的FPGA输入/输出架构

    公开(公告)号：US5625301A

    公开(公告)日：1997-04-29

    申请号：US444243

    申请日：1995-05-18

    申请人： William C. Plants ,  Sinan Kaptanoglu ,  Jung-Cheun Lien ,  King W. Chan ,  Khaled A. El-Ayat

    发明人： William C. Plants ,  Sinan Kaptanoglu ,  Jung-Cheun Lien ,  King W. Chan ,  Khaled A. El-Ayat

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17744 ,  H03K19/17704

    摘要： An input/output architecture for a field-programmable gate array integrated circuit including a plurality of logic function modules in an array of rows and columns, each of the modules having at least one input conductor and at least one output conductor; a plurality of interconnect conductors, comprising a plurality of input/output pads; a plurality of input/output kernels, each input/output kernel comprising an input buffer having a data input connected to one of the I/O pads and a data output connected to an input buffer data conductor, an output buffer having a data input connected to an output buffer data conductor, a data output connected to the I/O pad, and an enable input connected to an output buffer enable conductor; the input buffer data conductors extending in either the row or the column direction, different ones of the input buffer data conductors extending different numbers of rows or columns, the input buffer data conductors forming first intersections with inputs of the modules; the output buffer data conductors and output buffer enable conductors extending in either the row or the column direction, different ones of the output buffer data conductors and output buffer enable conductors extending different numbers of rows or columns, the input buffer data conductors forming second intersections with outputs of the modules; and user-programmable interconnect elements connected across selected ones of the first and second intersections.

    摘要翻译： 一种用于现场可编程门阵列集成电路的输入/输出架构，包括行和列阵列中的多个逻辑功能模块，每个模块具有至少一个输入导体和至少一个输出导体; 多个互连导体，包括多个输入/输出焊盘; 多个输入/输出内核，每个输入/输出内核包括输入缓冲器，该输入缓冲器具有连接到I / O焊盘之一的数据输入和连接到输入缓冲器数据导体的数据输出;输出缓冲器，其具有连接的数据输入 连接到输出缓冲器数据导体，连接到I / O焊盘的数据输出和连接到输出缓冲器使能导体的使能输入; 输入缓冲器数据导体在行或列方向上延伸，不同的输入缓冲器数据导体延伸不同数量的行或列，输入缓冲器数据导体与模块的输入形成第一交点; 输出缓冲器数据导体和输出缓冲器使能导体在行或列方向上延伸，不同的输出缓冲器数据导体和输出缓冲器使能导体延伸不同数量的行或列，输入缓冲器数据导体与第 模块输出; 以及连接在第一和第二交叉点中的选定的互连元件之间的用户可编程互连元件。

    High speed static RAM sensing system
    83.
    发明授权
    High speed static RAM sensing system 失效
    高速静态RAM感应系统

    公开(公告)号：US5068830A

    公开(公告)日：1991-11-26

    申请号：US349564

    申请日：1989-05-09

    申请人： William C. Plants ,  Scott N. Fritz

    发明人： William C. Plants ,  Scott N. Fritz

    IPC分类号： G11C7/06 ,  G11C11/419

    CPC分类号： G11C7/062 ,  G11C11/419 ,  G11C2207/063

    摘要： A current differential sense amplifier for static RAM cells which couple one of a pair of bit lines to a current source for a high speed read operation. The sense amplifier has current mirrors which amplify the current on each of the bit lines. The amplified currents are fed into an active load which has an output node which rises and falls in voltage depending upon the current mismatch. An inverter connected to the output node speeds the slow rate of the node.

    COMMON DOPED REGION WITH SEPARATE GATE CONTROL FOR A LOGIC COMPATIBLE NON-VOLATILE MEMORY CELL
    84.
    发明申请
    COMMON DOPED REGION WITH SEPARATE GATE CONTROL FOR A LOGIC COMPATIBLE NON-VOLATILE MEMORY CELL 有权
    具有独立门控的通用区域用于逻辑兼容的非易失性存储器单元

    公开(公告)号：US20130107635A1

    公开(公告)日：2013-05-02

    申请号：US13284795

    申请日：2011-10-28

    申请人： David Edward Fisch ,  William C. Plants ,  Michael Curtis Parris

    发明人： David Edward Fisch ,  William C. Plants ,  Michael Curtis Parris

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： H01L29/42324 ,  G11C16/00 ,  G11C16/0416 ,  H01L27/11558 ,  H01L29/7881

    摘要： An array of memory cells, in which one or more memory cells have a common doped region. Each memory cell includes a transistor with a floating gate, source and drain regions, and separate gate and drain voltage controls. Each memory cell also includes a coupling capacitor electrically coupled to and located laterally from the floating gate. In the array, first bit lines are oriented in a first direction, wherein a first bit line is coupled to drain regions of transistors that are arranged in a column. The array includes second bit lines also oriented in the first direction, wherein a second bit line is coupled to source regions of transistors that are arranged in a column. The array also includes word lines oriented in a second direction, wherein each word line is coupled to control gates of coupling capacitors that are arranged in a row.

    摘要翻译： 存储单元阵列，其中一个或多个存储单元具有公共掺杂区域。 每个存储单元包括具有浮置栅极，源极和漏极区域以及单独的栅极和漏极电压控制的晶体管。 每个存储器单元还包括电耦合到浮动栅极并且横向浮置的栅极的耦合电容器。 在阵列中，第一位线在第一方向上定向，其中第一位线耦合到排列在列中的晶体管的漏极区域。 该阵列包括也在第一方向上定向的第二位线，其中第二位线耦合到排列在列中的晶体管的源极区域。 阵列还包括在第二方向上定向的字线，其中每个字线耦合到排成一行的耦合电容器的控制栅极。

    Delay locked loop for an FPGA architecture
    87.
    发明授权
    Delay locked loop for an FPGA architecture 有权
    延迟锁定环路用于FPGA架构

    公开(公告)号：US07941685B2

    公开(公告)日：2011-05-10

    申请号：US12337201

    申请日：2008-12-17

    申请人： William C. Plants ,  Nikhil Mazumder ,  Arunangshu Kundu ,  James Joseph ,  Wayne W. Wong

    发明人： William C. Plants ,  Nikhil Mazumder ,  Arunangshu Kundu ,  James Joseph ,  Wayne W. Wong

    IPC分类号： G06F1/08

    CPC分类号： G06F1/10

    摘要： A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.

    摘要翻译： DLL提供了一种去偏移模式，用于将通过时钟分配树的参考时钟对准到反馈，通过向反馈时钟添加额外的延迟，将反馈时钟与参考时钟对齐在一个周期之后。 通过添加额外的延迟来将输入缓冲区考虑到反馈路径中，提供0 ns时钟到输出模式。 反馈时钟可以通过在反馈路径中布置的50％占空比调整的时钟倍增器加倍。 灵活的定时是将参考时钟对齐到反馈时钟，其通过设置在反馈和参考时钟路径中的附加延迟元件获得。

    FLEXIBLE CARRY SCHEME FOR FIELD PROGRAMMABLE GATE ARRAYS
    90.
    发明申请
    FLEXIBLE CARRY SCHEME FOR FIELD PROGRAMMABLE GATE ARRAYS 有权
    用于现场可编程门阵列的灵活执行方案

    公开(公告)号：US20100100864A1

    公开(公告)日：2010-04-22

    申请号：US12645863

    申请日：2009-12-23

    申请人： William C. Plants

    发明人： William C. Plants

    IPC分类号： G06F17/50

    CPC分类号： G06F7/506 ,  H03K19/17728

    摘要： A fast, flexible carry scheme for use in clustered field programmable gate array architectures is described. Each cluster has a cluster carry input node, a cluster carry output node, a cluster carry output circuit having an output coupled to the cluster carry output node, a first input coupled to the cluster carry input node, and a second input and a plurality of logic modules each comprising a logic function generator circuit coupled to a carry circuit. The logic modules are coupled in a series carry arrangement between the cluster carry input node and the second input of the cluster carry output circuit such that the least significant bit of an arithmetic logic circuit can be programmably placed in any of the logic modules.

    摘要翻译： 描述了用于集群现场可编程门阵列架构的快速，灵活的携带方案。 每个集群具有集群进位输入节点，集群进位输出节点，具有耦合到集群进位输出节点的输出的集群进位输出电路，耦合到集群进位输入节点的第一输入和第二输入和多个 每个逻辑模块包括耦合到进位电路的逻辑功能发生器电路。 逻辑模块以集群携带输入节点和集群携带输出电路的第二输入之间的串联进位装置耦合，使得算术逻辑电路的最低有效位可以可编程地置于任何逻辑模块中。