公开(公告)号：US20060253632A1

公开(公告)日：2006-11-09

申请号：US11399370

申请日：2006-04-07

Applicant: Shoji Yoshida ,  Kaoru Ishida ,  Hiroshi Yajima

Inventor： Shoji Yoshida ,  Kaoru Ishida ,  Hiroshi Yajima

IPC: G06F13/38

CPC classification number: H04B1/006 ,  H04W88/06

Abstract: A switching control circuit includes a serial-to-parallel converter, a rewritable storage device, and a decoder. The serial-to-parallel converter performs serial-to-parallel conversion for converting an inputted first control signal into a first parallel signal, and outputs the first parallel signal. The rewritable storage device has a write mode and a read mode selectively switched over in response to a storage mode switching signal, stores therein data of the first parallel signal in the write mode, and outputs the stored data as a second parallel signal in the read mode. In the read mode, the decoder decodes the first control signal and the second parallel signal to generate and output a plurality of element control signals to a plurality of elements, respectively. In the write mode, the decoder holds the plurality of element control signals generated in the read mode.

公开(公告)号：US07109578B2

公开(公告)日：2006-09-19

申请号：US11000204

申请日：2004-12-01

Applicant: Kaoru Ishida

Inventor： Kaoru Ishida

IPC: H01L23/12 ,  H01L23/04

CPC classification number: H05K1/0231 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L23/66 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/15173 ,  H01L2924/19105 ,  H05K1/112 ,  H05K2201/10522 ,  H05K2201/10674

Abstract: Crosstalk is suppressed low even when one surface of a multi-layer board seats a semiconductor integrated circuit of the BGA type and peripheral circuit components. Of a plurality of BGA bumps arranged on the back surface of a semiconductor integrated circuit chip, those BGA bumps (such as a high-frequency signal pin) to which peripheral circuit components need be mounted right close are arranged outer-most, and peripheral circuit components are then mounted right close to these BGA bumps. The BGA bumps one tier inner from the outer-most BGA bumps, which are to be used as grounding terminals, are connected with a wide inner-layer grounding wire pattern. Those BGA bumps (such as a logic control signal pin) to which peripheral circuit components need not be mounted right close are disposed further inward and connected with an inner-layer wire pattern which is located even deeper down from a front layer. This makes the grounding pattern held between the signal wire pattern and the control wire pattern and ensures isolation between these wire patterns, whereby it is possible to suppress leakage of a signal which could cause crosstalk.

Abstract translation: 即使多层板的一个表面位于BGA型半导体集成电路和外围电路部件上，串扰也被抑制得较低。 布置在半导体集成电路芯片的背面上的多个BGA凸块中，需要紧密安装外围电路部件的那些BGA凸点（例如高频信号引脚）被布置在最外侧，并且外围电路 然后将组件紧靠这些BGA凸块安装。 用作接地端子的最外面的BGA凸块内部的BGA凸点与宽内层接地线图案相连。 外围电路部件不需要紧密安装的那些BGA凸块（诸如逻辑控制信号引脚）进一步向内设置，并且与从前层更深地定位的内层线图形连接。 这使得在信号线图案和控制线图案之间保持接地图案，并且确保这些线图案之间的隔离，由此可以抑制可能引起串扰的信号的泄漏。

公开(公告)号：US07106766B2

公开(公告)日：2006-09-12

申请号：US10400981

申请日：2003-03-27

Applicant: Kaoru Ishida ,  Tsuguhiro Korenaga

Inventor： Kaoru Ishida ,  Tsuguhiro Korenaga

IPC: H01S3/04 ,  H01L23/34

CPC classification number: H01S5/02252 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01S5/0226 ,  H01S5/02276 ,  H01S5/0228 ,  H01S5/024 ,  H01S5/02438 ,  H01S5/4087 ,  H01L2924/00014

Abstract: In a conventional optical device which mounts a semiconductor light emitting element, the processing is difficult and a manufacturing process cost is expensive because of the necessity of forming via holes in a substrate.An optical device comprises a laser diode which needs heat radiation, a glass substrate which is integrally molded into a mold glass for arranging the laser diode, a metallic heat sink arranged at an edge of the glass substrate for radiating heat generated from the laser diode, wherein an active layer proximity surface of the laser diode is arranged to oppose the heat sink, both of them are connected with a conductive paste through a lateral groove formed in the glass substrate.

Abstract translation: 在安装半导体发光元件的常规光学器件中，由于需要在衬底中形成通孔，所以处理困难并且制造工艺成本昂贵。 光学装置包括需要散热的激光二极管，将整体模制成用于配置激光二极管的模具玻璃的玻璃基板，布置在玻璃基板的边缘处的用于辐射由激光二极管产生的热量的金属散热器， 其中激光二极管的有源层接近表面布置成与散热器相对，它们都通过形成在玻璃基板中的横向沟槽与导电浆料连接。

公开(公告)号：US07081795B2

公开(公告)日：2006-07-25

申请号：US11255998

申请日：2005-10-24

Applicant: Toru Matsuura ,  Kaoru Ishida ,  Makoto Sakakura ,  Seiji Fujiwara

Inventor： Toru Matsuura ,  Kaoru Ishida ,  Makoto Sakakura ,  Seiji Fujiwara

IPC: H03F1/26

CPC classification number: H03F1/3241 ,  H03F1/3229 ,  H03F1/3247 ,  H03F1/3276 ,  H03F1/3282

Abstract: An amplitude frequency characteristic adjustment circuit 106 is provided downstream of and connected to a distortion generation circuit 105. An amplitude difference between low-frequency-side and high-frequency-side distortion voltages is adjusted by the amplitude frequency characteristic adjustment circuit 106, and then their amplitudes and phases are adjusted by a vector adjustment circuit 107. This configuration makes it possible to suppress simultaneously both of low-frequency-side and high-frequency-side distortion voltages of a distortion generated by a wide-band class-AB power amplifier even if they are different in amplitude and phase.

公开(公告)号：US20060073857A1

公开(公告)日：2006-04-06

申请号：US11212732

申请日：2005-08-29

Applicant: Mikio Hanabusa ,  Kazunori Watanabe ,  Kaoru Ishida

Inventor： Mikio Hanabusa ,  Kazunori Watanabe ,  Kaoru Ishida

IPC: H04M1/00

CPC classification number: G07B15/063 ,  H04W52/0245 ,  Y02D70/142 ,  Y02D70/164

Abstract: A receiving device includes a receiver circuit for outputting a received signal as a reception electric field intensity signal, an operation control circuit for controlling an operation of the receiver circuit, and an intermittent reception control circuit for outputting a periodic signal. A comparator circuit holds a first threshold indicating that the receiving device has entered a communication area and a second threshold indicating a start of a continuous electric field intensity measurement. If the reception electric field intensity signal is lower than the second threshold, the operation control circuit makes the receiver circuit perform intermittent operation. If the reception electric field intensity signal is equal to or higher than the second threshold, the operation control circuit makes the receiver circuit perform a continuous operation. If the reception electric field intensity signal is equal to or higher than the first threshold, the operation control circuit makes the demodulation circuit perform an operation.

Abstract translation: 接收装置包括用于输出接收信号作为接收电场强度信号的接收机电路，用于控制接收机电路的操作的操作控制电路和用于输出周期性信号的间歇接收控制电路。 比较器电路保持指示接收装置已经进入通信区域的第一阈值和指示连续电场强度测量的开始的第二阈值。 如果接收电场强度信号低于第二阈值，则操作控制电路使接收机电路执行间歇操作。 如果接收电场强度信号等于或高于第二阈值，则操作控制电路使接收器电路执行连续操作。 如果接收电场强度信号等于或高于第一阈值，则操作控制电路使解调电路进行操作。

公开(公告)号：US20060061418A1

公开(公告)日：2006-03-23

申请号：US11255998

申请日：2005-10-24

Applicant: Toru Matsuura ,  Kaoru Ishida ,  Makoto Sakakura ,  Seiji Fujiwara

Inventor： Toru Matsuura ,  Kaoru Ishida ,  Makoto Sakakura ,  Seiji Fujiwara

IPC: H03F1/26

CPC classification number: H03F1/3241 ,  H03F1/3229 ,  H03F1/3247 ,  H03F1/3276 ,  H03F1/3282

Abstract: An amplitude frequency characteristic adjustment circuit 106 is provided downstream of and connected to a distortion generation circuit 105. An amplitude difference between low-frequency-side and high-frequency-side distortion voltages is adjusted by the amplitude frequency characteristic adjustment circuit 106, and then their amplitudes and phases are adjusted by a vector adjustment circuit 107. This configuration makes it possible to suppress simultaneously both of low-frequency-side and high-frequency-side distortion voltages of a distortion generated by a wide-band class-AB power amplifier even if they are different in amplitude and phase.

公开(公告)号：US06989713B2

公开(公告)日：2006-01-24

申请号：US11100507

申请日：2005-04-07

Applicant: Toru Matsuura ,  Kaoru Ishida ,  Makoto Sakakura ,  Seiji Fujiwara

Inventor： Toru Matsuura ,  Kaoru Ishida ,  Makoto Sakakura ,  Seiji Fujiwara

IPC: H03F1/26

CPC classification number: H03F1/3241 ,  H03F1/3229 ,  H03F1/3247 ,  H03F1/3276 ,  H03F1/3282

Abstract: An amplitude frequency characteristic adjustment circuit 106 is provided downstream of and connected to a distortion generation circuit 105. An amplitude difference between low-frequency-side and high-frequency-side distortion voltages is adjusted by the amplitude frequency characteristic adjustment circuit 106, and then their amplitudes and phases are adjusted by a vector adjustment circuit 107. This configuration makes it possible to suppress simultaneously both of low-frequency-side and high-frequency-side distortion voltages of a distortion generated by a wide-band class-AB power amplifier even if they are different in amplitude and phase.

Abstract translation: 幅度频率特性调整电路106设置在失真产生电路105的下游并连接到失真产生电路105。 通过幅度频率特性调整电路106调整低频侧和高频侧失真电压之间的幅度差，然后通过矢量调整电路107调整其幅度和相位。 通过这种结构，即使幅度和相位不同，也能同时抑制由宽带AB类功率放大器产生的失真的低频侧和高频侧的失真电压。

公开(公告)号：US06946926B2

公开(公告)日：2005-09-20

申请号：US10469032

申请日：2003-02-19

Applicant: Mikihiro Shimada ,  Kaoru Ishida ,  Hiroyuki Asakura

Inventor： Mikihiro Shimada ,  Kaoru Ishida ,  Hiroyuki Asakura

IPC: H05K3/46 ,  H01B11/00 ,  H01P3/00 ,  H01P3/02 ,  H01P3/08 ,  H04B3/32 ,  H05K1/00 ,  H05K1/02 ,  H01P3/04

CPC classification number: H01P3/026 ,  H01P3/023 ,  H05K1/0228 ,  H05K1/0237 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/09672

Abstract: A wired transmission path includes first and second differential transmission paths. The first differential transmission path is composed of two strip lines, and the second differential transmission path is composed of two strip lines. Each of the strip lines of the first differential transmission path is disposed at an equal distance from the strip lines of the second differential transmission path. Thus, there is provided a wired transmission path including a plurality of differential transmission paths in such a manner so as to cancel crosstalk.

Abstract translation: 有线传输路径包括第一和第二差分传输路径。 第一差分传输路径由两条带状线组成，第二差分传输路径由两条带状线组成。 第一差分传输路径的每条带状线设置在与第二差分传输路径的带状线相等的距离处。 因此，提供了一种包括多个差分传输路径的有线传输路径，以便消除串扰。

公开(公告)号：US20050139988A1

公开(公告)日：2005-06-30

申请号：US11000204

申请日：2004-12-01

Applicant: Kaoru Ishida

Inventor： Kaoru Ishida

IPC: H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H01L23/552 ,  H01L23/66 ,  H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H01L23/48

CPC classification number: H05K1/0231 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L23/66 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/15173 ,  H01L2924/19105 ,  H05K1/112 ,  H05K2201/10522 ,  H05K2201/10674

Abstract: Crosstalk is suppressed low even when one surface of a multi-layer board seats a semiconductor integrated circuit of the BGA type and peripheral circuit components. Of a plurality of BGA bumps arranged on the back surface of a semiconductor integrated circuit chip, those BGA bumps (such as a high-frequency signal pin) to which peripheral circuit components need be mounted right close are arranged outer-most, and peripheral circuit components are then mounted right close to these BGA bumps. The BGA bumps one tier inner from the outer-most BGA bumps, which are to be used as grounding terminals, are connected with a wide inner-layer grounding wire pattern. Those BGA bumps (such as a logic control signal pin) to which peripheral circuit components need not be mounted right close are disposed further inward and connected with an inner-layer wire pattern which is located even deeper down from a front layer. This makes the grounding pattern held between the signal wire pattern and the control wire pattern and ensures isolation between these wire patterns, whereby it is possible to suppress leakage of a signal which could cause crosstalk.

Abstract translation: 即使多层板的一个表面位于BGA型半导体集成电路和外围电路部件上，串扰也被抑制得较低。 布置在半导体集成电路芯片的背面上的多个BGA凸块中，需要紧密安装外围电路部件的那些BGA凸点（例如高频信号引脚）被布置在最外侧，并且外围电路 然后将组件紧靠这些BGA凸块安装。 用作接地端子的最外面的BGA凸块内部的BGA凸点与宽内层接地线图案相连。 外围电路部件不需要紧密安装的那些BGA凸块（诸如逻辑控制信号引脚）进一步向内设置，并且与从前层更深地定位的内层线图形连接。 这使得在信号线图案和控制线图案之间保持接地图案，并且确保这些线图案之间的隔离，由此可以抑制可能引起串扰的信号的泄漏。

公开(公告)号：US06710652B2

公开(公告)日：2004-03-23

申请号：US09961144

申请日：2001-09-21

Applicant: Masayuki Miyaji ,  Kaoru Ishida ,  Toshimitsu Matsuyoshi ,  Seiji Fujiwara

Inventor： Masayuki Miyaji ,  Kaoru Ishida ,  Toshimitsu Matsuyoshi ,  Seiji Fujiwara

IPC: H03F100

CPC classification number: H03F1/3229 ,  H03F2201/3218

Abstract: A feedforward amplifier includes a first power splitter for dividing an input signal into two paths. The first path, in sequence, includes a first vector adjuster, a main amplifier, a second power splitter and a delay circuit. The second path, in sequence, includes a delay circuit, a distortion detecting power combiner, a second vector adjuster and an error amplifier. The distortion detecting power combiner combines a portion of a signal from the first path with a signal in the second path. Each vector adjuster adjusts amplitude and phase of a signal in each path. A distortion suppression power combiner synthesizes a signal in the first path with a signal in the second path. Control is included for stopping operation of the error amplifier or main amplifier based on a predetermined condition.

Abstract translation: 前馈放大器包括用于将输入信号分成两个路径的第一功率分配器。 第一路径依次包括第一矢量调节器，主放大器，第二功率分配器和延迟电路。 第二路径依次包括延迟电路，失真检测功率组合器，第二矢量调节器和误差放大器。 失真检测功率组合器将来自第一路径的信号的一部分与第二路径中的信号组合。 每个矢量调节器调整每个路径中信号的幅度和相位。 失真抑制功率组合器将第一路径中的信号与第二路径中的信号合成。 包括用于基于预定条件停止误差放大器或主放大器的操作的控制。