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120 条记录 (耗时 0.044 秒)

    Clock synchronous type semiconductor memory device
    83.
    发明授权
    Clock synchronous type semiconductor memory device 有权
    时钟同步型半导体存储器件

    公开(公告)号：US06757212B2

    公开(公告)日：2004-06-29

    申请号：US10034544

    申请日：2002-01-03

    申请人： Takeshi Hamamoto ,  Takeo Miki

    发明人： Takeshi Hamamoto ,  Takeo Miki

    IPC分类号： G11C800

    CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/222

    摘要： A clock signal, which is generated by utilizing a delay circuit having a delay time depending on the operation frequency of an internal clock signal, is applied to a first circuit for activation thereof, and a clock signal, which has a fixed delay not dependent on the clock frequency and is adjusted in phase with respect to an external clock signal, is applied to a second circuit receiving the output signal of the first circuit for operation thereof. Thus, the operation timing of the second circuit can be set to be as late as possible. Consequently, it is possible to mitigate the operation conditions of the first circuit, to achieve a high speed data transfer. Even in the high speed operation, internal data can be reliably taken in, and transferred accurately.

    摘要翻译： 通过利用具有取决于内部时钟信号的工作频率的延迟时间的延迟电路产生的时钟信号被施加到第一电路以激活它，以及时钟信号，其具有不依赖于 时钟频率并相对于外部时钟信号被同相调节，被施加到接收第一电路的输出信号以用于其操作的第二电路。 因此，可以将第二电路的操作定时设置为尽可能晚。 因此，可以减轻第一电路的操作条件，以实现高速数据传输。 即使在高速运行中，内部数据也可以被可靠地接收并准确传送。

    Semiconductor memory device
    84.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US06597625B2

    公开(公告)日：2003-07-22

    申请号：US09976113

    申请日：2001-10-15

    申请人： Takanobu Suzuki ,  Takeshi Hamamoto

    发明人： Takanobu Suzuki ,  Takeshi Hamamoto

    IPC分类号： G11C800

    CPC分类号： G11C8/06

    摘要： A semiconductor memory device wherein, if an address-input buffer section 3 is arranged away from a central part of a memory chip 8, then a second address-latch circuit section 5 is arranged at a neighborhood of the address-input buffer section 3. By this means, the deterioration of the setup/hold characteristics in the address data IA[0-12] of the internal address signal due to coupling noise between wiring lines and the like can be prevented. A first address-latch circuit section 4 is arranged at a central part of the memory chip 8, so that delays in a bank-control signal for memory banks 2a to 2d and the like can be prevented. Further, if the address-input buffer section 3 is divided into a plurality of address-input buffers, for example, two buffers 3a and 3b, and arranged on the memory chip 8, then the second address-latch circuit section 5 is also divided into two address-latch circuits 5a and 5b, corresponding to the address-input buffers 3a and 3b, and the address-latch circuit 5a is arranged at a neighborhood of the address-input buffer 3a, and the address-latch circuit 5b is arranged at a neighborhood of the address-input buffer 3b.

    Pattern data density inspection apparatus and density inspection method and recording medium storing pattern data density inspection program
    85.
    发明授权
    Pattern data density inspection apparatus and density inspection method and recording medium storing pattern data density inspection program 失效
    图案数据密度检查装置和密度检查方法以及存储图案数据密度检查程序的记录介质

    公开(公告)号：US06505325B1

    公开(公告)日：2003-01-07

    申请号：US09615450

    申请日：2000-07-13

    申请人： Takeshi Hamamoto

    发明人： Takeshi Hamamoto

    IPC分类号： G06F945

    CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A pattern density inspection apparatus is provided which improves the detection accuracy of a pattern data density error region, and outputs detection results for a designer to efficiently perform a correction operation without performing detection of pattern data density error regions which do not require correction. A control section 1 reads out layout data from a layout storage section 2, and stores this in an input processing section 3 and an output processing section 7. A data density computation processing section 4, while displacing layout data of the input processing section 3 from a position where pattern data was computed immediately before, in either one of an X axis direction and a Y axis direction, performs computations of the pattern density in the detection range after movement, and judges if the pattern data density is above 50%, and makes that above 50% a temporary error region. An error overlap removal processing section 5 takes a logical sum of temporary error regions, and creates an aggregate temporary error region. An error region width computation processing section 6 judges if an aggregate temporary error region is an error shape which contains a 400 &mgr;m square error judgment reference shape.

    摘要翻译： 提供了图案密度检查装置，其提高了图案数据密度误差区域的检测精度，并且输出检测结果以使设计者有效地执行校正操作，而不执行不需要校正的图案数据密度误差区域的检测。 控制部分1从布局存储部分2读出布局数据，并将其存储在输入处理部分3和输出处理部分7中。数据密度计算处理部分4在将输入处理部分3的布局数据从 在X轴方向和Y轴方向中的任意一个之前立即计算图案数据的位置，进行运动后的检测范围内的图案密度的计算，判断图案数据密度是否在50％以上， 使超过50％的临时错误区域。 错误重叠移除处理部分5获取临时错误区域的逻辑和，并创建聚合临时错误区域。 误差区域宽度计算处理部6判断聚合暂时错误区域是否包含400μm的平方误差判定基准形状的误差形状。

    Synchronous semiconductor memory device capable of selecting column at high speed
    87.
    发明授权
    Synchronous semiconductor memory device capable of selecting column at high speed 失效

    公开(公告)号：US06333892B2

    公开(公告)日：2001-12-25

    申请号：US09725851

    申请日：2000-11-30

    申请人： Takeshi Hamamoto ,  Zenya Kawaguchi ,  Motoko Hara

    发明人： Takeshi Hamamoto ,  Zenya Kawaguchi ,  Motoko Hara

    IPC分类号： G11C800

    CPC分类号： G11C7/1072 ,  G11C8/18

    摘要： A command decoder receives an externally supplied command independently of an internal clock signal, decodes the command, generates a column access mode instruction signal, and activates a column address activation signal when the internal clock signal rises. An internal column address signal generating circuit generates an internal column address signal from an externally supplied address signal according to the column address activation signal. Accordingly, the internal column address is generated at an advanced timing to enable a following column selecting operation to be started at a faster timing. A synchronous semiconductor memory device capable of performing the column selecting operation at a high speed is thus provided.

    Figure operation of layout for high speed processing
    88.
    发明授权
    Figure operation of layout for high speed processing 失效
    图高速处理布局图

    公开(公告)号：US06189129B1

    公开(公告)日：2001-02-13

    申请号：US09092650

    申请日：1998-06-09

    申请人： Takeshi Hamamoto

    发明人： Takeshi Hamamoto

    IPC分类号： G06F1750

    CPC分类号： G06F17/5081

    摘要： In a method of processing figure arrays in a figure processing apparatus, first and second figure arrays are sequentially inputted. A fractionalizing process is selectively performed to divide each of figure elements of the second figure array into a plurality of types of fractions based on presence/non-presence of an overlapping portion between the first and second figure arrays and an array data of the second figure array. The array data indicates an array pitch in each of horizontal and vertical directions and a number of figures in the direction. A figure array of fractions is produced for each type and the produced figure arrays is registered in chain groups which includes a chain group of the first figure array, such that the registered figure arrays have the same array data. Then, a figure operating process is performed to the chain group.

    摘要翻译： 在图形处理装置中处理图形阵列的方法中，依次输入第一和第二图形阵列。 选择性地执行分数化过程，以基于第一和第二图形数组之间的重叠部分的存在/不存在以及第二图形的阵列数据的不同，将第二图形数组的图形元素中的每一个划分成多种类型的分数 数组。 阵列数据表示水平和垂直方向中的每一个中的阵列间距和方向上的数量。 为每种类型生成图形数组的分数，并且所生成的图形数组被记录在包括第一图形数组的链组的链组中，使得注册的图形数组具有相同的数组数据。 然后，对链组进行图形操作处理。

    Semiconductor memory device having hierarchical word line structure
    89.
    发明授权
    Semiconductor memory device having hierarchical word line structure 失效
    具有分层字线结构的半导体存储器件

    公开(公告)号：US6157588A

    公开(公告)日：2000-12-05

    申请号：US229343

    申请日：1999-01-13

    申请人： Yasuhiro Matsumoto ,  Mikio Asakura ,  Takeshi Hamamoto ,  Kei Hamade

    发明人： Yasuhiro Matsumoto ,  Mikio Asakura ,  Takeshi Hamamoto ,  Kei Hamade

    IPC分类号： G11C11/407 ,  G11C7/18 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/02

    CPC分类号： G11C7/18 ,  G11C11/4097

    摘要： First and second global input/output lines are twisted between first and second main blocks. First and second SD signal lines in the first main block are respectively arranged adjacent to first and second global input/output lines. First and second SD signal lines in the second main block are respectively arranged adjacent to the second and first global input/output lines. An SD signal supplied for the first or second SD signal line makes noises applied to the first and second global input/output lines identical, so that an influence by the noises is substantially eliminated between the first and second global input/output lines. As a result, the global input/output line is provided with higher resistance to noise without any increase in a layout area.

    摘要翻译： 第一和第二全局输入/输出线在第一和第二主块之间扭转。 第一主块中的第一和第二SD信号线分别布置成与第一和第二全局输入/输出线相邻。 第二主块中的第一和第二SD信号线分别布置成与第二和第一全局输入/输出线相邻。 为第一或第二SD信号线提供的SD信号对第一和第二全局输入/输出线施加相同的噪声，使得在第一和第二全局输入/输出线之间基本上消除了噪声的影响。 因此，全球输入/输出线路具有更高的抗噪声能力，而不会增加布局面积。

    Semiconductor memory device having trench-type capacitor structure using high dielectric film and its manufacturing method
    90.
    发明授权
    Semiconductor memory device having trench-type capacitor structure using high dielectric film and its manufacturing method 失效
    具有使用高介电膜的沟槽型电容器结构的半导体存储器件及其制造方法

    公开(公告)号：US6043528A

    公开(公告)日：2000-03-28

    申请号：US806247

    申请日：1997-02-21

    申请人： Masami Aoki ,  Takeshi Hamamoto

    发明人： Masami Aoki ,  Takeshi Hamamoto

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10861 ,  H01L27/10829 ,  H01L27/10873 ,  Y10S257/908

    摘要： A semiconductor memory device comprises a MOS-type transistor formed on a semiconductor substrate, a capacitor formed in the interior of an opening portion formed in the semiconductor substrate to be adjacent to the MOS-type transistor, the capacitor having a capacitor insulating film formed of a high dielectric film, and a line layer for connecting respective gate electrodes of the MOS-type transistor separated to be island-shaped to prevent from being presented on a region where the opening portion is formed, the line layer formed of a conductive layer different from the gate electrodes in its level.

    摘要翻译： 一种半导体存储器件，包括形成在半导体衬底上的MOS型晶体管，形成在与半导体衬底中形成的与MOS型晶体管相邻的开口部内部的电容器，该电容器具有由 高电介质膜和用于连接分离为岛状的MOS型晶体管的各个栅电极的线层，以防止形成在开口部分的区域上，由不同的导电层形成的线层 从门电极的电平。