公开(公告)号：US6057729A

公开(公告)日：2000-05-02

申请号：US94022

申请日：1998-06-09

申请人： Masahiro Nomura

发明人： Masahiro Nomura

IPC分类号： H01L27/04 ,  G05F1/56 ,  G06F1/30 ,  H01L21/822 ,  H01L27/08 ,  H03B1/04

CPC分类号： H01L27/08 ,  G06F1/305 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/13091 ,  H01L2924/3011

摘要： A power circuit for an integrated circuit chip having a plurality of operation frequency modes, the power circuit varying a resonance point defined by a parasitic resistance, inductance and capacitance existing in a power supplying line, in accordance with an operation frequency to thereby prevent the operation frequency from being in accord with a resonance frequency. For instance, when the operation frequency is relatively high, the power circuit lowers the resonance point, and when the operation frequency is relatively low, the power circuit raises the resonance point. The power circuit may further include an encoder receiving an operation frequency mode signal, and emitting an output signal indicative of an operation frequency. The power circuit provides a power ensuring stable operation of an external circuit in a plurality of operation frequency modes.

摘要翻译： 一种用于具有多个工作频率模式的集成电路芯片的电源电路，所述电源电路根据操作频率改变由供电线路中存在的寄生电阻，电感和电容所限定的谐振点，从而防止操作 频率与谐振频率一致。 例如，当操作频率相对较高时，电源电路降低谐振点，并且当操作频率相对较低时，电源电路提高谐振点。 电源电路还可以包括接收操作频率模式信号的编码器，以及发出指示操作频率的输出信号。 电源电路提供了确保在多种操作频率模式中外部电路的稳定操作的功率。

公开(公告)号：US6001862A

公开(公告)日：1999-12-14

申请号：US292955

申请日：1999-04-16

申请人： Toshio Maeda ,  Masahiro Nomura ,  Katsuya Awano ,  Susumu Kinoshita ,  Hiroya Satoh ,  Koji Murakami ,  Masaki Tsunoda

发明人： Toshio Maeda ,  Masahiro Nomura ,  Katsuya Awano ,  Susumu Kinoshita ,  Hiroya Satoh ,  Koji Murakami ,  Masaki Tsunoda

IPC分类号： C07D277/34 ,  C07D417/12 ,  A61K31/425

CPC分类号： C07D417/12 ,  C07D277/34

摘要： The present invention provides novel N-benzyldioxothiazolidylbenzamide derivatives that improve the insulin resistance and have potent hypoglycemic and lipid-lowering effects and processes for preparing the same, and relates to N-benzyldioxothiazolidylbenzamide derivatives characterized by being represented by a general formula (1) ##STR1## [wherein R.sup.1 and R.sup.2 denote identically or differently hydrogen atoms, lower alkyl groups with carbon atoms of 1 to 4, lower alkoxy groups with carbon atoms of 1 to 3, lower haloalkyl groups with carbon atoms of 1 to 3, lower haloalkoxy groups with carbon atoms of 1 to 3, halogen atoms, hydroxyl groups, nitro groups, amino groups which may be substituted with lower alkyl group(s) with carbon atoms of 1 to 3 or hetero rings, or R.sup.1 and R.sup.2 link to form a methylenedioxy group, R.sup.3 denotes a lower alkoxy group with carbon atoms of 1 to 3, hydroxyl group or halogen atom, and dotted line indicates double bond or single bond in combination with solid line], and processes for preparing the same.

摘要翻译： 本发明提供了改善胰岛素抵抗并具有强效降血糖和降脂作用的新型N-苄基二硫代噻唑烷基苯甲酰胺衍生物及其制备方法，涉及以通式（1）表示的N-苄基二硫代噻唑烷基苯甲酰胺衍生物[其中 R1和R2表示相同或不同的氢原子，碳原子数为1〜4的低级烷基，碳原子数1〜3的低级烷氧基，碳原子数1〜3的低级卤代烷基，碳原子数为1〜 1至3，卤素原子，羟基，硝基，可被具有1至3个碳原子的低级烷基取代的氨基或杂环，或R 1和R 2连接形成亚甲二氧基，R 3表示 碳原子数为1〜3的低级烷氧基，羟基或卤素原子，虚线表示双键或单键与实线组合]，工序 准备相同。

公开(公告)号：US5668484A

公开(公告)日：1997-09-16

申请号：US306981

申请日：1994-09-16

申请人： Masahiro Nomura

发明人： Masahiro Nomura

IPC分类号： G06F1/10 ,  H03K17/693 ,  H03K19/01

CPC分类号： G06F1/10

摘要： A clock signal distribution circuit of a tree structure having a plurality of buffers arranged in a plurality of hierarchical stages includes short-circuit wirings for short-circuiting output terminals of the buffers at each stage of the plurality of hierarchical stages. Each of the plurality of buffers is formed by a single inverter or a multi-stage inverter wherein an input stage inverter and an output stage inverter are connected in series. The output stage inverter has a size larger than that of the input stage inverter. The clock signal distribution circuit thus constructed can reduce clock skew and distribute a high frequency clock signal having sharp rise and fall characteristics to a plurality of registers.

摘要翻译： 具有以多个分层级布置的多个缓冲器的树结构的时钟信号分配电路包括用于在多个分层级的每个阶段使缓冲器的输出端短路的短路布线。 多个缓冲器中的每一个由单个反相器或多级反相器形成，其中输入级反相器和输出级反相器串联连接。 输出级反相器的尺寸大于输入级反相器的尺寸。 如此构造的时钟信号分配电路可以减少时钟偏移并且将具有尖锐上升和下降特性的高频时钟信号分配给多个寄存器。

公开(公告)号：US20130181872A1

公开(公告)日：2013-07-18

申请号：US13824136

申请日：2011-09-07

申请人： Eiichi Furukawa ,  Masahiro Nomura

发明人： Eiichi Furukawa ,  Masahiro Nomura

IPC分类号： H01Q1/24

CPC分类号： H01Q1/24 ,  H01P3/12 ,  H01P11/002 ,  H04B1/40

摘要： The purpose of the present invention is to reduce the cost of a product while ensuring reliability of the product as a wireless transmission/reception apparatus. Provided is communication apparatus (ODU) (1) installed outside, which includes a case that houses a transmission unit for transmitting a signal and a reception unit for receiving the signal, and a waveguide connected to an external antenna and configured to receive/transmit a signal. In the apparatus, the waveguide is formed integrally with the case, and taper (16) is formed in a part of the tube hole of the waveguide.

摘要翻译： 本发明的目的是在确保作为无线发送/接收装置的产品的可靠性的同时降低产品的成本。 提供了安装在外部的通信装置（ODU）（1），其包括容纳用于发送信号的发送单元的壳体和用于接收信号的接收单元，以及连接到外部天线并被配置为接收/发送 信号。 在该装置中，波导与壳体一体地形成，并且在波导的管孔的一部分中形成有锥形部（16）。

公开(公告)号：US08390313B2

公开(公告)日：2013-03-05

申请号：US13052400

申请日：2011-03-21

申请人： Yoshifumi Ikenaga ,  Masahiro Nomura

发明人： Yoshifumi Ikenaga ,  Masahiro Nomura

IPC分类号： H03K19/00 ,  G01R25/00

CPC分类号： H03K19/00392

摘要： When an operation of a specified one of monitor circuits is defective or any of elements forming a ring oscillator in each of the monitor circuits has characteristic abnormality, if voltage control is performed based on a result from the monitor operating at a lowest speed, a required voltage may be overestimated. This results in an increase in power consumption, and also causes an accuracy reduction when the average value of detection results from the multiple monitors is calculated. The multiple monitor circuits are provided. Of the detection results therefrom, any detection result falling outside a predetermined range is ignored, and the average value of the remaining monitor results is used as a final monitor detection value.

摘要翻译： 当监视电路中指定的一个监视器电路的操作有故障或每个监视器电路中形成环形振荡器的元件中的任何元件具有特征异常时，如果基于监视器以最低速度操作的结果进行电压控制， 电压可能被高估了。 这导致功耗的增加，并且当计算来自多个监视器的检测结果的平均值时，也导致精度降低。 提供多个监视器电路。 在其检测结果中，忽略超出预定范围的任何检测结果，并且将剩余监视结果的平均值用作最终监视检测值。

公开(公告)号：US08386988B2

公开(公告)日：2013-02-26

申请号：US13005289

申请日：2011-01-12

申请人： Masahiro Nomura

发明人： Masahiro Nomura

IPC分类号： H03H11/26 ,  G06F17/50

CPC分类号： G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  H03K3/0315 ,  Y02D10/126 ,  Y02D10/172

摘要： A semiconductor integrated circuit includes a first circuit part that is designed under a first corner condition with respect to a process variation, a second circuit part that is designed under a second corner condition narrower than the first condition, and a control part that changes an operating voltage supplied to the first circuit part and the second circuit part according to a delay amount of the first circuit part, and starts the second circuit part when a delay characteristic caused by a change in the operating voltage conforms to a delay characteristic under the second corner condition.

摘要翻译： 一种半导体集成电路包括：第一电路部分，其被设计在相对于工艺变化的第一角状态下;第二电路部分被设计在比第一条件窄的第二角状态;以及控制部分，其改变操作 根据第一电路部分的延迟量提供给第一电路部分和第二电路部分的电压，并且当由于工作电压的变化引起的延迟特性符合第二角下的延迟特性时启动第二电路部分 条件。

公开(公告)号：US20110241725A1

公开(公告)日：2011-10-06

申请号：US13052400

申请日：2011-03-21

申请人： Yoshifumi IKENAGA ,  Masahiro Nomura

发明人： Yoshifumi IKENAGA ,  Masahiro Nomura

IPC分类号： H03K19/00 ,  G01R25/00

CPC分类号： H03K19/00392

摘要： When an operation of a specified one of monitor circuits is defective or any of elements forming a ring oscillator in each of the monitor circuits has characteristic abnormality, if voltage control is performed based on a result from the monitor operating at a lowest speed, a required voltage may be overestimated. This results in an increase in power consumption, and also causes an accuracy reduction when the average value of detection results from the multiple monitors is calculated. The multiple monitor circuits are provided. Of the detection results therefrom, any detection result falling outside a predetermined range is ignored, and the average value of the remaining monitor results is used as a final monitor detection value.

摘要翻译： 当监视电路中指定的一个监视器电路的操作有故障或每个监视器电路中形成环形振荡器的元件中的任何元件具有特征异常时，如果基于监视器以最低速度操作的结果执行电压控制，则所需的 电压可能被高估了。 这导致功耗的增加，并且当计算来自多个监视器的检测结果的平均值时，也导致精度降低。 提供多个监视器电路。 在其检测结果中，忽略超出预定范围的任何检测结果，并且将剩余监视结果的平均值用作最终监视检测值。

公开(公告)号：US08004348B2

公开(公告)日：2011-08-23

申请号：US12526988

申请日：2008-02-14

申请人： Yoshifumi Ikenaga ,  Masahiro Nomura

发明人： Yoshifumi Ikenaga ,  Masahiro Nomura

IPC分类号： G05F1/10

CPC分类号： H03K19/00384

摘要： A control circuit controls a power-source-voltage feed circuit, and controls a power source voltage fed to a target circuit. A reference-speed monitor monitors whether or not a delay time of a critical path in the target circuit is satisfies a required operational speed. A voltage-difference monitor monitors a difference between the power source voltage of the target circuit and a threshold voltage of the target circuit, to output the voltage difference information. The control circuit determines whether to increase or decrease the power source voltage based on a result of monitoring by the reference-speed monitor. The control circuit determines the change rate of the power source voltage so that the control rate of the power source voltage is proportional to the voltage difference information output from the voltage-difference monitor.

摘要翻译： 控制电路控制电源电压馈电电路，并控制馈送到目标电路的电源电压。 参考速度监视器监视目标电路中的关键路径的延迟时间是否满足所需的操作速度。 电压差监视器监视目标电路的电源电压与目标电路的阈值电压之间的差异，以输出电压差信息。 控制电路根据基准速度监视器的监视结果来决定是否增加或减小电源电压。 控制电路确定电源电压的变化率，使得电源电压的控制速率与从电压差监视器输出的电压差信息成比例。

公开(公告)号：US07960035B2

公开(公告)日：2011-06-14

申请号：US11909724

申请日：2006-03-30

申请人： Shinji Kozuma ,  Masahiro Nomura ,  Ikuro Hashimoto

发明人： Shinji Kozuma ,  Masahiro Nomura ,  Ikuro Hashimoto

IPC分类号： B32B3/00 ,  B32B5/00 ,  B32B15/00 ,  B32B15/18 ,  B32B15/20

CPC分类号： C21D9/46 ,  C22C38/00 ,  C22C38/06 ,  C22C38/58 ,  C23C22/12 ,  C23G1/08 ,  Y10T428/12979 ,  Y10T428/12993 ,  Y10T428/26

摘要： There is provided a high-strength hot rolled steel sheet excellent in phosphatability, wherein a maximum depth (Ry) of pits and bumps, existing on a surface thereof, is not less than 10 μm, and an average interval (Sm) of the pits and the bumps is not more than 30 μm, meeting either a requirement for a load length ratio (tp40) of the pits and the bumps on the surface at not more than 20%, or a requirement for a difference between a load length ratio (tp60) and the load length ratio (tp40), at not less than 60%, or both thereof. The high-strength hot rolled steel sheet is capable of exhibiting stable and excellent phosphatability even if Mo highly effective for reinforcement in strength is added thereto in expectation of a higher strength.

摘要翻译： 提供了优异的磷酸化性的高强度热轧钢板，其中存在于其表面上的凹坑和凸块的最大深度（Ry）不小于10μm，并且凹坑的平均间隔（Sm） 并且凸起不大于30μm，满足对凹坑的负载长度比（tp40）和表面上的凸块的要求不大于20％，或者要求负载长度比（ tp60）和负载长度比（tp40），不小于60％，或其两者。 高强度热轧钢板即使在强度高的情况下也能够高效地加强强化，能够表现出稳定且优异的磷酸化性。

公开(公告)号：US20100117705A1

公开(公告)日：2010-05-13

申请号：US12588993

申请日：2009-11-04

申请人： Masahiro Nomura

发明人： Masahiro Nomura

IPC分类号： H03H11/26

CPC分类号： H03K5/135 ,  H03K5/26

摘要： A plurality of delay paths are connected in parallel between two synchronous operation circuits operating in synchronism with a clock signal CLK, and enable transmission of a signal. A delay detection unit detects the respective delay times of the plurality of delay paths, and a control unit selects one delay path from among the plurality of delay paths based on the detection results from the delay detection unit, and controls the blocking of signal transmission in the delay paths other than the selected one delay path.

摘要翻译： 多个延迟路径并联连接在与时钟信号CLK同步操作的两个同步操作电路之间，并且使能信号的传输。 延迟检测单元检测多个延迟路径的各个延迟时间，并且控制单元基于来自延迟检测单元的检测结果从多个延迟路径中选择一个延迟路径，并且控制信号传输阻塞 除了所选择的一个延迟路径之外的延迟路径。