Systems and Methods for Reverse Pulsing
    81.
    发明申请

    公开(公告)号:US20170372912A1

    公开(公告)日:2017-12-28

    申请号:US15701176

    申请日:2017-09-11

    Abstract: Systems and methods for reverse pulsing are described. One of the methods includes receiving a digital signal having a first state and a second state. The method further includes generating a transformer coupled plasma (TCP) radio frequency (RF) pulsed signal having a high state when the digital signal is in the first state and having a low state when the digital signal is in the second state. The method includes providing the TCP RF pulsed signal to one or more coils of a plasma chamber, generating a bias RF pulsed signal having a low state when the digital signal is in the first state and having a high state when the digital signal is in the second state, and providing the bias RF pulsed signal to a chuck of the plasma chamber.

    Methods and systems for plasma etching using bi-modal process gas composition responsive to plasma power level

    公开(公告)号:US09691625B2

    公开(公告)日:2017-06-27

    申请号:US14932265

    申请日:2015-11-04

    CPC classification number: H01L21/3065 H01L21/3081 H01L21/31116

    Abstract: A substrate is disposed on a substrate holder within a process module. The substrate includes a mask material overlying a target material with at least one portion of the target material exposed through an opening in the mask material. A bi-modal process gas composition is supplied to a plasma generation region overlying the substrate. For a first period of time, a first radiofrequency power is applied to the bi-modal process gas composition to generate a plasma to cause etching-dominant effects on the substrate. For a second period of time, after completion of the first period of time, a second radiofrequency power is applied to the bi-modal process gas composition to generate the plasma to cause deposition-dominant effects on the substrate. The first and second radiofrequency powers are applied in an alternating and successive manner for an overall period of time to remove a required amount of exposed target material.

    ELECTROSTATIC CHUCK WITH THERMAL CHOKE

    公开(公告)号:US20170098566A1

    公开(公告)日:2017-04-06

    申请号:US14875473

    申请日:2015-10-05

    CPC classification number: H01L21/6833 H01L21/67109

    Abstract: Apparatuses, systems, and techniques for providing enhanced electrostatic chucks are provided. Such apparatuses, systems, and techniques may include, for example, a common RF and DC electrode in an electrostatic chuck, connection, at a location external to a semiconductor processing chamber, of a high-voltage DC power source and a high-voltage RF power source to a common conductive pathway leading to an electrostatic chuck in the interior of the semiconductor processing chamber, a very thin dielectric layer located on an upper surface of an electrostatic chuck, and/or an axial thermal choke that may be used to control heat flow within an electrostatic chuck.

    INTERNAL PLASMA GRID FOR SEMICONDUCTOR FABRICATION
    84.
    发明申请
    INTERNAL PLASMA GRID FOR SEMICONDUCTOR FABRICATION 审中-公开
    用于半导体制造的内部等离子体网格

    公开(公告)号:US20140302681A1

    公开(公告)日:2014-10-09

    申请号:US14082009

    申请日:2013-11-15

    Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid may have slots of a particular aspect ratio which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The lower sub-chamber plasma has a lower electron density, lower effective electron temperature, and higher negative ion:positive ion ratio as compared to the upper sub-chamber plasma. The disclosed embodiments may result in an etching process having good center to edge uniformity, selectivity, profile angle, and Iso/Dense loading.

    Abstract translation: 这里公开的实施例涉及用于蚀刻半导体衬底的改进的方法和设备。 等离子体栅格位于反应室中,以将室分成上部和下部子室。 等离子格栅可以具有特定纵横比的槽,其允许某些物质从上部子室穿过到下部子室。 在一些情况下,在上部子室中产生电子 - 离子等离子体。 使其通过栅格到下部子室的电子在它们通过时被冷却。 在某些情况下,这导致下部子室中的离子离子等离子体。 与上部小室等离子体相比,下部小室等离子体具有较低的电子密度,较低的有效电子温度和较高的负离子:正离子比。 所公开的实施例可以导致具有良好的中心到边缘均匀性,选择性,轮廓角和Iso / Dense加载的蚀刻工艺。

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