公开(公告)号：US06468877B1

公开(公告)日：2002-10-22

申请号：US09907651

申请日：2001-07-19

申请人： Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung

发明人： Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung

IPC分类号： H01L2176

CPC分类号： H01L21/7682 ,  H01L21/764 ,  H01L21/823468 ,  H01L29/4983

摘要： A method of fabricating an air-gap spacer of a semiconductor device, comprising the following steps. A semiconductor substrate having at least a pair of STIs defining an active region is provided. A gate electrode is formed on the substrate within the active region. The gate electrode having an underlying gate dielectric layer. A liner oxide layer is formed over the structure, covering the sidewalls of the gate dielectric layer, the gate electrode, and over the top surface of the gate electrode. A liner nitride layer is formed over the liner oxide layer. A thick oxide layer is formed over the structure. The thick oxide, liner nitride, and liner oxide layers are planarized level with the top surface of the gate electrode, and exposing the liner oxide layer at either side of the gate electrode. The planarized thick oxide layer is removed with a portion of the liner oxide layer and a portion of the gate dielectric layer under the gate electrode to form a cross-section inverted T-shaped opening on either side of the gate electrode. A gate spacer oxide layer is formed over the structure at least as thick as the gate electrode, wherein the gate spacer oxide layer partially fills the inverted T-shaped opening from the top down and wherein air gap spacers are formed proximate the bottom of the inverted T-shaped opening. The gate spacer oxide, liner nitride, and liner oxide layers are etched to form gate spacers proximate the gate electrode. The gate spacers having an underlying etched liner nitride layer and liner oxide layer.

摘要翻译： 一种制造半导体器件的气隙间隔物的方法，包括以下步骤。 提供具有至少一对限定有源区域的STI的半导体衬底。 在有源区内的基板上形成栅电极。 栅电极具有底层栅介电层。 在该结构上形成衬里氧化物层，覆盖栅极电介质层的侧壁，栅电极以及栅电极的顶表面。 在衬垫氧化物层上形成衬里氮化物层。 在结构上形成厚的氧化物层。 厚氧化物，衬里氮化物和衬里氧化物层与栅电极的顶表面平坦化，并且在栅电极的任一侧暴露衬里氧化物层。 用一部分衬垫氧化物层和栅电介质层的一部分在栅电极下方去除平坦化的厚氧化物层，以在栅电极的任一侧上形成横截面倒置的T形开口。 在该结构上形成至少与栅电极一样厚的栅极间隔氧化物层，其中栅极间隔物氧化物层从顶部向下部分地填充倒置的T形开口，并且其中气隙间隔物邻近倒置的底部形成 T形开口。 蚀刻栅间隔氧化物，衬里氮化物和衬里氧化物层以在栅电极附近形成栅极间隔。 栅极间隔物具有下面的蚀刻衬里氮化物层和衬里氧化物层。

公开(公告)号：US06455377B1

公开(公告)日：2002-09-24

申请号：US09765040

申请日：2001-01-19

申请人： Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep

发明人： Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep

IPC分类号： H01L21336

CPC分类号： H01L29/66666 ,  H01L29/1054 ,  H01L29/66916 ,  H01L29/7827 ,  H01L29/802

摘要： A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench. A gate conductor layer is formed on the gate dielectric layer, filling the gate trench.

摘要翻译： 一种制造垂直沟道晶体管的方法，包括以下步骤。 提供具有上表面的半导体衬底。 在半导体衬底上形成高掺杂N型下部外延硅层。 在下部外延硅层上形成低掺杂P型中间外延硅层。 在中间外延硅层上形成高掺杂N型上部外延硅层。 蚀刻下部，中间和上部外延硅层以形成由隔离沟槽限定的外延层堆叠。 在隔离槽内形成氧化物。 氧化物被蚀刻以在一个隔离沟槽内形成栅极沟槽，暴露外延层堆叠面向栅极沟槽的侧壁。 在暴露的外延层堆叠侧壁上形成多量子阱或染色层超晶格。 在多量子阱或染色层超晶格上并在栅极沟槽内形成栅介质层。 栅极导体层形成在栅极电介质层上，填充栅极沟槽。

公开(公告)号：US06440800B1

公开(公告)日：2002-08-27

申请号：US09769814

申请日：2001-01-26

申请人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

发明人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

IPC分类号： H01L21336

CPC分类号： H01L29/66666 ,  H01L29/365 ,  H01L29/7827

摘要： A method for a vertical transistor by selective epi deposition to form the conductive source, drain, and channel layers. The conductive source, drain, and channel layers are preferably formed by a selective epi process. Dielectric masks define the conductive layers and make areas to form vertical contacts to the conductive S/D and channel layers.

公开(公告)号：US06387747B1

公开(公告)日：2002-05-14

申请号：US09867561

申请日：2001-05-31

申请人： Randall Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Chua Chee Tee

发明人： Randall Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Chua Chee Tee

IPC分类号： H01L218244

CPC分类号： H01L28/10 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method for forming an RF inductor of helical shape having high Q and minimum area. The inductor is fabricated of metal or damascened linear segments formed on three levels of intermetal dielectric layers and interconnected by metal filled vias to form the complete helical shape with electrical continuity.

摘要翻译： 一种形成具有高Q值和最小面积的螺旋形RF电感器的方法。 电感器由形成在三层金属间电介质层上并由金属填充的通孔相互连接形成具有电连续性的完整螺旋形状的金属或镶嵌的线性段制成。

公开(公告)号：US06384437B1

公开(公告)日：2002-05-07

申请号：US09963411

申请日：2001-09-27

申请人： Kheng Chok Tee ,  Randall Cher Liang Cha ,  Lap Chan

发明人： Kheng Chok Tee ,  Randall Cher Liang Cha ,  Lap Chan

IPC分类号： H01L27148

CPC分类号： H01L27/10873 ,  H01L27/10808

摘要： Low current leakage DRAM structures are achieved using a selective silicon epitaxial growth over an insulating layer on memory cell (device) areas. An insulating layer, that also serves as a stress-release layer, and a Si3N4 hard mask are patterned to leave portions over the memory cell areas. Shallow trenches are etched in the substrate and filled with a CVD oxide which is polished back to the hard mask to form shallow trench isolation (STI) around the memory cell areas. The hard mask is selectively removed to form recesses in the STI aligned over the memory cell areas exposing the underlying insulating layer. Openings are etched in the insulating layer to provide a silicon-seed surface from which is grown a selective epitaxial layer extending over the insulating layer within the recesses. After growing a gate oxide on the epitaxial layer, FETs and DRAM capacitors can be formed on the epitaxial layer. The insulating layer under the epitaxial layer drastically reduces the capacitor leakage current and improves DRAM device performance. This self-aligning method also increases memory cell density, and is integratable into current DRAM processes to reduce cost.

摘要翻译： 使用在存储器单元（器件）区域上的绝缘层上的选择性硅外延生长来实现低电流泄漏DRAM结构。 也用作应力释放层的绝缘层和Si 3 N 4硬掩模被图案化以在存储器单元区域上留下部分。 在衬底中蚀刻浅沟槽，并填充有CVD氧化物，其被抛光回硬掩模以在存储器单元区域周围形成浅沟槽隔离（STI）。 选择性地去除硬掩模，以在STI暴露下面的绝缘层的存储单元区域上对准STI中形成凹槽。 在绝缘层中蚀刻开口以提供硅种子表面，从该晶种表面生长在凹陷内的绝缘层上延伸的选择性外延层。 在外延层上生长栅极氧化物之后，可以在外延层上形成FET和DRAM电容器。 外延层下方的绝缘层大大降低了电容器的漏电流，提高了DRAM器件性能。 这种自对准方法也增加了存储单元密度，并且可以集成到当前的DRAM工艺中以降低成本。

公开(公告)号：US06281117B1

公开(公告)日：2001-08-28

申请号：US09425994

申请日：1999-10-25

申请人： Lap Chan ,  Chaw Sing Ho ,  Fong Yau Sam Li ,  Hou Tee Ng

发明人： Lap Chan ,  Chaw Sing Ho ,  Fong Yau Sam Li ,  Hou Tee Ng

IPC分类号： H01L214763

CPC分类号： H01L21/28518 ,  Y10S977/859

摘要： A method for forming uniform ultrathin silicide features in the fabrication of an integrated circuit is described. A metal layer is deposited over the surface of a silicon semiconductor substrate. An array of heated metallic tips contact the metal layer whereby the metal layer is transformed to a metal silicide where it is contacted by the metallic tips and wherein the metal layer not contacted by the metallic tips is unreacted. The unreacted metal layer is removed leaving the metal silicide as uniform ultrathin silicide features. Alternatively, a metal acetate layer is spin-coated over the surface of a silicon semiconductor substrate. An array of heated metallic tips contacts the metal acetate layer whereby the metal acetate layer is transformed to a metal silicide where the metallic tips contact the metal acetate layer and wherein the metal acetate slayer not contacted by the metallic tips is unreacted. Or the metal acetate layer is heat treated at localized regions using a multi-array of tips aligned in a specific layout. Or the metal acetate layer is contacted by heated metallic tips under vacuum so that the metal does not oxidize. The unreacted metal acetate layer is removed leaving the metal silicide as the uniform ultrathin silicide features.

摘要翻译： 描述了在制造集成电路中形成均匀的超薄硅化物特征的方法。 金属层沉积在硅半导体衬底的表面上。 加热的金属尖端的阵列接触金属层，由此将金属层转变为金属硅化物，在金属硅化物中金属层与金属顶端接触，并且其中不与金属尖端接触的金属层是未反应的。 除去未反应的金属层，留下金属硅化物作为均匀的超薄硅化物特征。 或者，将金属乙酸盐层旋涂在硅半导体衬底的表面上。 加热的金属尖端的阵列接触金属乙酸盐层，由此金属乙酸盐层转变为金属硅化物，其中金属尖端与金属乙酸盐层接触，并且其中未与金属尖端接触的金属乙酸盐钝化剂未反应。 或者使用在特定布局中对齐的多阵列尖端在局部区域对金属乙酸盐层进行热处理。 或者金属乙酸盐层在真空下被加热的金属尖端接触，使得金属不氧化。 除去未反应的金属乙酸盐层，留下金属硅化物作为均匀的超薄硅化物特征。

公开(公告)号：US06261935B1

公开(公告)日：2001-07-17

申请号：US09458725

申请日：1999-12-13

申请人： Alex See ,  Lap Chan ,  Ravi Sundaresan

发明人： Alex See ,  Lap Chan ,  Ravi Sundaresan

IPC分类号： H01L214763

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76895 ,  H01L29/66545 ,  H01L29/6656

摘要： A new method is provided for the creation of contact pads to the poly gate of MOS devices. STI regions are formed, layers of gate oxide, poly and SiN are deposited. The poly gate is patterned and etched leaving a layer of SiN on the surface of the gate. An oxide liner is created, an LDD implant is performed, the gate spacers are created and source/drain region implants are performed. A layer of titanium is deposited and annealed, a salicide etchback is performed to the layer of titanium creating silicided surfaces over the source and drain regions. Inter level dielectric (ILD) is deposited, the layer of ILD is polished down to the SiN layer on the top surface of the gate. The layer of SiN is removed creating a recessed gate structure. A stack of layers of titanium-amorphous silicon-titanium (Ti/Si/Ti) or a layer of WSix is deposited over the layer of ILD filling the recess on top of the gate with Ti/Si/Ti. This Ti/Si/Ti (or WSix) is patterned and etched forming a Ti/Si/Ti stack (or layer of WSix) that partially overlays the layer of ILD while also penetrating the recessed opening of the gate electrode. The layer of Ti/Si/Ti is silicided and forms the contact pad to the gate structure.

摘要翻译： 提供了一种用于向MOS器件的多晶硅栅极创建接触焊盘的新方法。 形成STI区，沉积栅氧化层，聚和SiN层。 多晶硅栅极被图案化和蚀刻，在栅极的表面上留下一层SiN层。 产生氧化物衬垫，执行LDD注入，产生栅极间隔物并执行源极/漏极区域注入。 沉积并退火一层钛，对源层和漏极区产生硅化表面的钛层进行自对准硅蚀刻蚀刻。 层间电介质（ILD）被沉积，ILD层被抛光到栅极顶表面上的SiN层。 去除SiN层，产生凹陷的栅极结构。 在TiD / Si / Ti上在栅极顶部填充凹槽的ILD层上沉积一叠钛 - 非晶硅 - 钛（Ti / Si / Ti）或一层WSix层。 该Ti / Si / Ti（或WSix）被图案化和蚀刻形成Ti / Si / Ti叠层（或WSix层），其部分覆盖ILD层，同时也穿过栅电极的凹入开口。 Ti / Si / Ti层被硅化并形成与栅极结构的接触焊盘。

公开(公告)号：US06252277B1

公开(公告)日：2001-06-26

申请号：US09392392

申请日：1999-09-09

申请人： Lap Chan ,  Cher Liang Cha ,  Eng Fong Chor ,  Gong Hao ,  Teck Koon Lee

发明人： Lap Chan ,  Cher Liang Cha ,  Eng Fong Chor ,  Gong Hao ,  Teck Koon Lee

IPC分类号： H01L2972

CPC分类号： H01L29/66621 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7834

摘要： Formation of a MOSFET with a polysilicon gate electrode embedded within a silicon trench is described. The MOSFET retains all the features of conventional MOSFETs with photolithographically patterned polysilicon gate electrodes, including robust LDD (lightly doped drain) regions formed in along the walls of the trench. Because the gate dielectric is never exposed to plasma etching or aqueous chemical etching, gate dielectric films of under 100 Angstroms may be formed without defects. The problems of over etching, and substrate spiking which are encountered in the manufacture of photolithographically patterned polysilicon gate electrodes do not occur. The entire process utilizes only two photolithographic steps. The first step defines the silicon active area by patterning a field isolation and the second defines a trench within the active area wherein the device is formed. The new process, uses the same total number of photolithographic steps to form the MOSFET device elements as a conventional process but is far more protective of the thin gate oxide.

摘要翻译： 描述了形成具有嵌入在硅沟槽内的多晶硅栅电极的MOSFET。 MOSFET保留了具有光刻图案化多晶硅栅电极的常规MOSFET的所有特征，包括沿沟槽壁形成的鲁棒LDD（轻掺杂漏极）区域。 因为栅极电介质永远不会暴露于等离子体蚀刻或水性化学蚀刻，所以可以形成低于100埃的栅介质膜而没有缺陷。 在光刻图案化多晶硅栅电极的制造中遇到的过蚀刻和衬底尖峰的问题不会发生。 整个过程仅使用两个光刻步骤。 第一步骤通过图案化场隔离来定义硅有源面积，第二步限定在形成器件的有源区域内的沟槽。 新工艺使用相同的光刻步骤总数来形成MOSFET器件元件作为常规工艺，但对薄栅极氧化物的保护更为广泛。

公开(公告)号：US06251798B1

公开(公告)日：2001-06-26

申请号：US09359894

申请日：1999-07-26

申请人： Choi Pheng Soo ,  Kheng Chok Tee ,  Kok Keng Ong ,  Lap Chan

发明人： Choi Pheng Soo ,  Kheng Chok Tee ,  Kok Keng Ong ,  Lap Chan

IPC分类号： H01L2131

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for the formation of an air gap structure for use in inter-metal applications. A metal pattern of metal lines is formed, a layer of Plasma Polymerized Methylsilane (PPMS) resist is deposited on top of this pattern. The surface of the PPMS resist is subjected to selective exposure. The unexposed PPMS is removed after which the process is completed by closing up the openings within the PPMS.

摘要翻译： 一种用于形成用于金属间应用的气隙结构的方法。 形成金属线的金属图案，在该图案的顶部上沉积一层等离子聚合甲基硅烷（PPMS）抗蚀剂。 对PPMS抗蚀剂的表面进行选择性曝光。 未曝光的PPMS被去除，之后通过关闭PPMS内的开口来完成该过程。

公开(公告)号：US06251781B1

公开(公告)日：2001-06-26

申请号：US09374312

申请日：1999-08-16

申请人： Mei Sheng Zhou ,  Guo-Qin Xu ,  Lap Chan

发明人： Mei Sheng Zhou ,  Guo-Qin Xu ,  Lap Chan

IPC分类号： H01L2144

CPC分类号： H01L21/76874 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating single and dual damascene copper interconnects is achieved. A semiconductor substrate layer is provided. Conductive traces are provided in an isolating dielectric layer. An intermetal dielectric layer is deposited overlying the conductive traces and the isolating dielectric layer. The intermetal dielectric layer is patterned to form trenches to expose the top surfaces of the underlying conductive traces. A barrier layer is deposited overlying the intermetal dielectric layer, the exposed conductive traces, and within the trenches. A platinum ionic seed solution is coated inside the trenches and overlying the barrier layer. A platinum seed layer is deposited from the ionic seed solution by exposing the platinum ionic seed solution to ultraviolet light. A copper layer is deposited by electroless plating to form copper interconnects, where the copper layer is only deposited overlying the platinum seed layer in the trenches, and where the deposition stops before the copper layer fills the trenches. The exposed barrier layer is polished down to the top surface of the intermetal dielectric layer. An encapsulation layer is deposited overlying the copper interconnects and the intermetal dielectric layer to complete the fabrication of the integrated circuit device.

摘要翻译： 实现了制造单和双镶嵌铜互连的方法。 提供半导体衬底层。 导电迹线设置在隔离电介质层中。 沉积覆盖导电迹线和隔离电介质层的金属间电介质层。 图案化金属间电介质层以形成沟槽以暴露下面的导电迹线的顶表面。 覆盖在金属间电介质层，暴露的导电迹线和沟槽内的阻挡层被沉积。 将铂离子种子溶液涂覆在沟槽内并覆盖阻挡层。 通过将铂离子种子溶液暴露于紫外光，从离子种子溶液沉积铂种子层。 通过无电镀沉积铜层以形成铜互连，其中铜层仅沉积在沟槽中的铂种子层上方，并且在铜层填充沟槽之前沉积停止。 暴露的阻挡层被抛光到金属间电介质层的顶表面。 沉积覆盖在铜互连和金属间电介质层上的封装层，以完成集成电路器件的制造。