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公开(公告)号：US20220236951A1
公开(公告)日：2022-07-28
申请号：US17344500
申请日：2021-06-10
Applicant: MACRONIX International Co., Ltd.
Inventor： Po-Hao Tseng , Feng-Min Lee , Yu-Hsuan Lin
Abstract: A multiplication and addition operation device and a control method thereof are provided. The multiplication and addition operation device includes a feature information filter and an in-memory calculator. The feature information filter records a plurality of designated bits of a plurality of feature information, compares received input information with the designated bits to generate a comparison result, and generates a selected address according to the comparison result. The in-memory calculator records all bits of the feature information, and generates an operation result by performing a multiplication and addition operation on the feature information and the input information according to the selected address.
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公开(公告)号：US20220108748A1
公开(公告)日：2022-04-07
申请号：US17065516
申请日：2020-10-07
Applicant: MACRONIX International Co., Ltd.
Inventor： Po-Hao Tseng , Ming-Hsiu Lee , Feng-Min Lee
IPC: G11C15/04
Abstract: A ternary content addressable memory and a memory cell thereof are provided. The ternary content addressable memory cell includes a first transistor and a second transistor. The first transistor has a gate to receive a selection signal. A first end of the first transistor is coupled to a match line. A second end of the first transistor is coupled to a source line. The second transistor has a gate to receive an inverted selection signal. A first end of the second transistor is coupled to the match line. A second end of the second transistor is coupled to the source line. The first and second transistors have charge storage structures.
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公开(公告)号：US10719296B2
公开(公告)日：2020-07-21
申请号：US15873369
申请日：2018-01-17
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Feng-Min Lee , Yu-Yu Lin
IPC: G06F7/544 , H03K19/17704 , G11C16/04 , G11C11/54 , H01L27/1157 , H01L27/11524 , H01L45/00
Abstract: A device for generating sum-of-products data includes an array of variable resistance cells, variable resistance cells in the array each comprising a programmable threshold transistor and a resistor connected in parallel, the array including n columns of cells including strings of series-connected cells and m rows of cells. Control and bias circuitry are coupled to the array, including logic for programming the programmable threshold transistors in the array with thresholds corresponding to values of a weight factor Wmn for the corresponding cell. Input drivers are coupled to corresponding ones of the m rows of cells, the input drivers selectively applying inputs Xm to rows m. Column drivers are configured to apply currents In to corresponding ones of the n columns of cells. Voltage sensing circuits operatively coupled to the columns of cells.
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84.发明授权公开(公告)号：US10482953B1
公开(公告)日：2019-11-19
申请号：US16103022
申请日：2018-08-14
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Hsuan Lin , Yu-Yu Lin , Feng-Min Lee , Chao-Hung Wang , Po-Hao Tseng , Kai-Chieh Hsu
Abstract: A multi-state memory device includes a first memory element, a second memory element, a first controlling element and a second controlling element. The second memory element has a memory cell structure identical to that of the first memory element and connects to the first memory element in series. The first controlling element is connected to the first memory element either in series or in parallel. The second controlling element has a characteristic value identical to that of the first controlling element and is connected to the second memory element by a connection structure identical to that of the first controlling element. When the first memory element receives a first signal and a second signal through the first controlling element, a first state value and a second state value are generated correspondingly, and the characteristic value is greater than the first state value and less than the second state value.
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公开(公告)号：US20190067574A1
公开(公告)日：2019-02-28
申请号：US15690353
申请日：2017-08-30
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu Lin , Feng-Min Lee , Po-Hao Tseng , Kai-Chieh Hsu
CPC classification number: H01L45/1641 , G11C13/0007 , G11C13/0069 , G11C13/0097 , G11C2013/0083 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/147 , H05K3/3494
Abstract: A method for treating a semiconductor structure is provided. A semiconductor structure comprising memory devices is provided. A forming process is conducted to initialize operation of the memory devices. The semiconductor structure is subjected to a forming thermal treatment, and step of saving data to the memory devices is performed after the forming thermal treatment.
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Patent Agency Ranking
86.发明授权公开(公告)号：US09959928B1
公开(公告)日：2018-05-01
申请号：US15377071
申请日：2016-12-13
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Kai-Chieh Hsu , Feng-Min Lee , Yu-Yu Lin
CPC classification number: G11C13/0064 , G11C13/0007 , G11C13/0069 , G11C2013/0085 , G11C2013/0088 , G11C2013/0092 , G11C2213/79
Abstract: A method to program a programmable resistance memory cell includes performing one or more iterations until a verifying passes. The iterations include a) applying a programming pulse to the memory cell, and, b) after applying the programming pulse, verifying if the resistance of the memory cell is in a target resistance range. After an iteration of the one or more iterations in which the verifying passes, c) a stabilizing pulse with a polarity the same as the programming pulse is applied to the memory cell. After applying the stabilizing pulse, a second verifying determines if the resistance of the programmable element is in the target resistance range. Iterations comprising steps a), b), c), and d) are performed until the second verifying passes. Methods and apparatus are described to program a plurality of such cells, including applying a stabilizing pulse of the same polarity after programming.
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公开(公告)号：US09859336B1
公开(公告)日：2018-01-02
申请号：US15401155
申请日：2017-01-09
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Po-Hao Tseng , Feng-Min Lee
IPC: H01L27/24 , H01L45/00 , H01L23/528 , H01L23/522
CPC classification number: H01L27/2463 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
Abstract: A semiconductor device including a memory cell structure is provided, and the memory cell structure includes an insulating layer disposed above a substrate, a bottom electrode embedded in the insulating layer, a resistance switching layer disposed on the bottom electrode, and a top electrode disposed on the resistance switching layer and covering the resistance switching layer. Also, the bottom electrode has a concave top surface lower than a flat upper surface of the insulating layer.
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公开(公告)号：US09853215B1
公开(公告)日：2017-12-26
申请号：US15365985
申请日：2016-12-01
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Po-Hao Tseng , Feng-Min Lee
IPC: H01L45/00
CPC classification number: H01L45/1266 , H01L45/08
Abstract: A resistance switching memory device is provided, including an insulating layer having a top surface, a bottom electrode embedded in the insulating layer, a resistance switching layer disposed on the bottom electrode, and a top electrode formed on the resistance switching layer and covering the resistance switching layer. Also, the bottom electrode has an upper portion protruding from the top surface of the insulating layer, and the upper portion has round corners at edges.
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89.发明申请公开(公告)号：US20170179384A1
公开(公告)日：2017-06-22
申请号：US14977770
申请日：2015-12-22
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Feng-Min Lee , Yu-Yu Lin
IPC: H01L45/00
CPC classification number: H01L45/1233 , H01L45/04 , H01L45/146 , H01L45/1608 , H01L45/1633
Abstract: A memory structure and a manufacturing method for the same are disclosed. The memory structure comprises a lower electrode, an upper insulating layer, a material layer, a dielectric film, and an upper electrode. The upper insulating layer is on the lower electrode. The material layer is on the upper insulating layer. The upper insulating layer and the material layer have a common opening to expose a portion of the lower electrode. The dielectric film is on the exposed portion of the lower electrode. The dielectric film and the material layer contain a same first transition metal. The upper electrode is on the dielectric film and fills the common opening.
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公开(公告)号：US20170047514A1
公开(公告)日：2017-02-16
申请号：US14825209
申请日：2015-08-13
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu Lin , Feng-Min Lee
IPC: H01L45/00
CPC classification number: H01L45/1633 , H01L45/08 , H01L45/1233 , H01L45/146
Abstract: A method for manufacturing a resistive memory device is disclosed and comprises following steps. Firstly, a bottom electrode is formed over a substrate. Next, an oxidation process is performed to the bottom electrode to form a metal oxide layer, wherein a hydrogen plasma and an oxygen plasma are provided during the oxidation process. Then, a top electrode is formed on the metal oxide layer.
Abstract translation: 公开了一种制造电阻式存储器件的方法，包括以下步骤。 首先，在基板上形成底部电极。 接下来，对底部电极进行氧化处理以形成金属氧化物层，其中在氧化过程中提供氢等离子体和氧等离子体。 然后，在金属氧化物层上形成顶部电极。
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