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    APPARATUSES AND METHODS FOR STORING AND WRITING MULTIPLE PARAMETER CODES FOR MEMORY OPERATING PARAMETERS
    81.
    发明申请
    APPARATUSES AND METHODS FOR STORING AND WRITING MULTIPLE PARAMETER CODES FOR MEMORY OPERATING PARAMETERS 审中-公开

    公开(公告)号：US20180211695A1

    公开(公告)日：2018-07-26

    申请号：US15933167

    申请日：2018-03-22

    Applicant: Micron Technology, Inc.

    Inventor： Dean D. Gans ,  Daniel C. Skinner

    IPC: G11C7/10

    CPC classification number: G11C7/1045 ,  G11C7/109

    Abstract: Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

    Apparatuses and methods for implementing masked write commands
    83.
    发明授权
    Apparatuses and methods for implementing masked write commands 有权
    用于实现屏蔽写入命令的设备和方法

    公开(公告)号：US09508409B2

    公开(公告)日：2016-11-29

    申请号：US14254378

    申请日：2014-04-16

    Applicant: Micron Technology, Inc.

    Inventor： Mark K. Hadrick ,  Jeffrey P. Wright ,  Victor Wong ,  Simon J. Lovett ,  Donald M. Morgan ,  William F. Jones ,  Sujeet Ayyapureddi ,  Dean D. Gans ,  Jongtae Kwak

    IPC: G11C7/22 ,  G11C7/10 ,  G11C8/12

    CPC classification number: G11C7/22 ,  G11C7/1009 ,  G11C7/1042 ,  G11C8/12 ,  G11C2207/229

    Abstract: Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.

    Abstract translation: 本文公开了用于实现屏蔽写入命令的装置和方法。 示例性装置可以包括存储体，局部缓冲电路和地址控制电路。 本地缓冲电路可以与存储体相关联。 地址控制电路可以耦合到存储体并被配置为接收命令和与该命令相关联的地址。 地址控制电路可以包括被配置为存储地址的全局缓冲电路。 地址控制电路还可以被配置为至少部分地基于写等待时间来延迟使用多个命令路径之一的命令，并且将存储在全局缓冲器电路中的地址提供给要存储的本地缓冲器电路 其中。

    Prefetch management for memory
    84.
    发明授权
    Prefetch management for memory 有权

    公开(公告)号：US11822477B2

    公开(公告)日：2023-11-21

    申请号：US17183225

    申请日：2021-02-23

    Applicant: Micron Technology, Inc.

    Inventor： Robert Nasry Hasbun ,  Dean D. Gans ,  Sharookh Daruwalla

    IPC: G06F12/0862 ,  G06F13/20

    CPC classification number: G06F12/0862 ,  G06F13/20 ,  G06F2212/1028 ,  G06F2212/6022 ,  G06F2212/652

    Abstract: Methods, systems, and devices are described for wireless communications. A request for data located in a memory page of a memory array may be received at a device, and a value of a prefetch counter associated with the memory page may be identified. A portion of the memory page that includes the requested data may then be communicated between a memory array and memory bank of the device based on the value of the prefetch counter. For instance, the portion of the memory page may be selected based on the value of the prefetch counter. A second portion of the memory page may be communicated to a buffer of the device, and the value of the prefetch counter may be modified based on a relationship between the first portion of the memory page and the second portion of the memory page.

    Prefetch signaling in memory system or subsystem
    86.
    发明授权
    Prefetch signaling in memory system or subsystem 有权

    公开(公告)号：US11604606B2

    公开(公告)日：2023-03-14

    申请号：US17307651

    申请日：2021-05-04

    Applicant: Micron Technology, Inc.

    Inventor： Robert Nasry Hasbun ,  Dean D. Gans ,  Sharookh Daruwalla

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for prefetch signaling in a memory system or sub-system are described. A memory device (e.g., a local memory controller of memory device) of a main memory may transmit a prefetch indicator indicating a size of prefetch data associated with a first set of data requested by an interface controller. The size of the prefetch data may be equal to or different than the size of the first set of data. The main memory may, in some examples, store the size of prefetch data along with the first set of data. The memory device may transmit the prefetch indicator (e.g., an indicator signal) to the interface controller using a pin compatible with an industry standard or specification and/or a separate pin configured for transmitting command or control information. The memory device may transmit the prefetch indicator while the first set of data is being transmitted.

    Stacked memory dice for combined access operations
    87.
    发明授权
    Stacked memory dice for combined access operations 有权

    公开(公告)号：US11599474B2

    公开(公告)日：2023-03-07

    申请号：US17538269

    申请日：2021-11-30

    Applicant: Micron Technology, Inc.

    Inventor： Dean D. Gans

    IPC: G06F12/0862 ,  G06F13/16 ,  H01L25/065 ,  G11C11/4093

    Abstract: Methods, systems, and devices for stacked memory dice and combined access operations are described. A device may include multiple memory dice. One die may be configured as a master, and another may be configured as a slave. The master may communicate with a host device. A slave may be coupled with the master but not the host device. The device may include a first die (e.g., master) and a second die (e.g., slave). The first die may be coupled with a host device and configured to output a set of data in response to a read command. The first die may supply a first subset of the data and obtain a second subset of the data from the second die. In some cases, the first die may select, based on a data rate, a modulation scheme (e.g., PAM4, NRZ, etc.) and output the data using the selected modulation scheme.

    Methods for activity-based memory maintenance operations and memory devices and systems employing the same
    88.
    发明授权
    Methods for activity-based memory maintenance operations and memory devices and systems employing the same 有权

    公开(公告)号：US11550650B2

    公开(公告)日：2023-01-10

    申请号：US16707151

    申请日：2019-12-09

    Applicant: Micron Technology, Inc.

    Inventor： Dean D. Gans

    IPC: G06F11/00 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02 ,  G11C11/22 ,  G11C29/04 ,  G06F13/16

    Abstract: Memory devices and methods of operating memory devices in which maintenance operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., operations in excess of a predetermined threshold) warrants a maintenance operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of operations at the memory location, to schedule a maintenance operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled maintenance operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further operations at the memory location until after the count has been decreased.

    Memory system and operations of the same
    89.
    发明授权
    Memory system and operations of the same 有权

    公开(公告)号：US11429291B2

    公开(公告)日：2022-08-30

    申请号：US17193248

    申请日：2021-03-05

    Applicant: Micron Technology, Inc.

    Inventor： Dean D. Gans

    IPC: G06F3/06 ,  G06F12/0802

    Abstract: Methods, systems, and devices related to a memory system or scheme that includes a first memory device configured for low-energy access operations and a second memory device configured for storing high-density information and operations of the same are described. The memory system may include an array configured for high-density information and may interface with a host via a controller and a cache or another array of a relatively fast memory type. The memory system may support signals communicated according to one or several modulation schemes, including a modulation scheme or schemes that employ two, three, or more voltage levels (e.g., NRZ, PAM4). The memory system may include, e.g., separate channels configured to communicate using different modulation schemes between a host and between memory arrays or memory types within the memory system.

    Memory buffer management and bypass
    90.
    发明授权
    Memory buffer management and bypass 有权

    公开(公告)号：US11340830B2

    公开(公告)日：2022-05-24

    申请号：US16932032

    申请日：2020-07-17

    Applicant: Micron Technology, Inc.

    Inventor： Robert Nasry Hasbun ,  Dean D. Gans ,  Sharookh Daruwalla

    IPC: G06F3/06 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/02

    Abstract: Methods, systems, and devices for memory buffer management and bypass are described. Data corresponding to a page size of a memory array may be received at a virtual memory bank of a memory device, and a value of a counter associated with the virtual memory bank may be incremented. Upon determining that a value of the counter has reached a threshold value, the data may be communicated from the virtual memory bank to a buffer of the same memory device. For instance, the counter may be incremented based on the virtual memory bank receiving an access command from a host device.

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