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    Self-refresh arbitration
    81.
    发明授权
    Self-refresh arbitration 有权

    公开(公告)号：US12204780B2

    公开(公告)日：2025-01-21

    申请号：US17660195

    申请日：2022-04-21

    Applicant: Micron Technology, Inc.

    Inventor： Mark Kalei Hadrick ,  Yu-Sheng Hsu ,  John Christopher Sancon ,  Kang-Yong Kim ,  Yang Lu

    IPC: G06F3/06

    Abstract: Described apparatuses and methods relate to self-refresh arbitration. In a memory system with multiple memory components, an arbiter is configured to manage the occurrence of self-refresh operations. In aspects, the arbiter can receive one or more self-refresh request signals from at least one memory controller for authorization to command one or more memory components to enter a self-refresh mode. Upon receiving the one or more self-refresh request signals, the arbiter, based on a predetermined configuration, can transmit one or more self-refresh enable signals to the at least one memory controller with authorization to command the one or more memory components to enter the self-refresh mode. The configuration can ensure that fewer than all memory components simultaneously enter the self-refresh mode. In so doing, memory components can perform self-refresh operations without exceeding an instantaneous power threshold. The arbiter can be included in, for instance, a Compute Express Link™ (CXL™) memory module.

    Programmable column access
    82.
    发明授权
    Programmable column access 有权

    公开(公告)号：US12183419B2

    公开(公告)日：2024-12-31

    申请号：US17648403

    申请日：2022-01-19

    Applicant: Micron Technology, Inc.

    Inventor： Hyunyoo Lee ,  Kang-Yong Kim ,  Taeksang Song

    IPC: G11C7/10 ,  G11C8/06 ,  G11C11/4074

    Abstract: Methods, systems, and devices for programmable column access are described. A device may transfer voltages from memory cells of a row in a memory array to respective digit lines for the memory cells. The voltages may be indicative of logic values stored at the memory cells. The device may communicate respective control signals to a set of multiplexers coupled with the digit lines, where each multiplexer is coupled with a respective subset of the digit lines. Each multiplexer may couple a digit line of the respective subset of digit lines with a respective sense component for that multiplexer based on the respective control signal for that multiplexer.

    Control Circuitry for Scheduling Aspects of Usage-Based Disturbance Mitigation Based on Different External Commands
    83.
    发明申请
    Control Circuitry for Scheduling Aspects of Usage-Based Disturbance Mitigation Based on Different External Commands 有权

    公开(公告)号：US20240404576A1

    公开(公告)日：2024-12-05

    申请号：US18642144

    申请日：2024-04-22

    Applicant: Micron Technology, Inc.

    Inventor： Yang Lu ,  Kang-Yong Kim ,  Mark Kalei Hadrick

    IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4096

    Abstract: Apparatuses and methods for scheduling aspects of usage-based disturbance mitigation based on different external commands are described. An apparatus comprises a memory device, which has at least one bank comprising memory cells. A subset of the memory cells is configured to store data associated with usage-based disturbance. The apparatus includes circuitry configured to mitigate usage-based disturbance within the bank. The memory device is configured to receive, from a memory controller, two commands that are separated in time by a timing offset. The memory device is configured to generate an internal read command based on the first command to cause the memory device to read the data from the subset of the memory cells. The memory device is configured to generate an internal write command based on the second command to cause the memory device to write modified data generated by the circuitry to the subset of the memory cells.

    Conflict Avoidance for Bank-Shared Circuitry that supports Usage-Based Disturbance Mitigation
    85.
    发明公开
    Conflict Avoidance for Bank-Shared Circuitry that supports Usage-Based Disturbance Mitigation 审中-公开

    公开(公告)号：US20240338126A1

    公开(公告)日：2024-10-10

    申请号：US18627859

    申请日：2024-04-05

    Applicant: Micron Technology, Inc.

    Inventor： Kang-Yong Kim ,  Yang Lu ,  Wonjun Choi ,  Mark Kalei Hadrick

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0673

    Abstract: Apparatuses and techniques for implementing collision avoidance for bank-shared circuitry that supports usage-based disturbance mitigation are described. A memory device includes bank-shared circuitry coupled to multiple banks. The bank-shared circuitry can support usage-based disturbance mitigation. By using the bank-shared circuitry to service multiple banks, the memory device can have a smaller footprint and can be cheaper to manufacture compared to other memory devices with circuitry dedicated for each bank. To avoid conflicts associated with some sequences of commands that may relate to a same bank or different banks and utilize the bank-shared circuitry, the memory controller applies an appropriate timing offset (or delay) between commands. The timing offset allows the memory device time to finish utilizing the bank-shared circuitry for usage-based disturbance mitigation prior to utilizing the bank-shared circuitry in accordance with a subsequent command.

    Memory Die Interconnections to Physical Layer Interfaces
    87.
    发明公开
    Memory Die Interconnections to Physical Layer Interfaces 审中-公开

    公开(公告)号：US20240202145A1

    公开(公告)日：2024-06-20

    申请号：US18540427

    申请日：2023-12-14

    Applicant: Micron Technology, Inc.

    Inventor： Yang Lu ,  Kang-Yong Kim

    IPC: G06F13/16 ,  G06F13/42

    CPC classification number: G06F13/1684 ,  G06F13/1689 ,  G06F13/4234

    Abstract: This disclosure describes aspects of memory die interconnections to physical layer interfaces (PHYs) that may enable expanded channel bus width and improved signal integrity (SI). In aspects, a memory die is operably coupled to a first PHY via a command-and-address (CA) bus and data input/output (DQ) bus of the first PHY and to a second PHY via a chip select (CS) bus of the second PHY. The second PHY may provide a CS signal to the memory die, and the first PHY can perform a training procedure via CA signaling or DQ signaling. The training procedure may improve SI between the memory die and the PHYs. Additionally, a memory die may be interconnected to different PHYs to expand a channel bus width. Thus, by interconnecting memory dies to one or more PHYs as described herein, improved SI and expanded channel bus width can be achieved.

    Apparatuses and methods including multilevel command and address signals
    88.
    发明授权
    Apparatuses and methods including multilevel command and address signals 有权

    公开(公告)号：US11923038B2

    公开(公告)日：2024-03-05

    申请号：US17805272

    申请日：2022-06-03

    Applicant: Micron Technology, Inc.

    Inventor： Kang-Yong Kim

    IPC: G11C7/10 ,  G11C8/10 ,  G11C8/18

    CPC classification number: G11C7/1084 ,  G11C7/106 ,  G11C7/1057 ,  G11C7/1087 ,  G11C8/10 ,  G11C8/18

    Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.

    Programmable memory timing
    89.
    发明授权
    Programmable memory timing 有权

    公开(公告)号：US11894099B2

    公开(公告)日：2024-02-06

    申请号：US17562560

    申请日：2021-12-27

    Applicant: Micron Technology, Inc.

    Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

    IPC: G06F13/16 ,  G11C7/22 ,  G11C7/10 ,  G06F3/06 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/10

    CPC classification number: G11C7/1087 ,  G06F3/0679 ,  G06F13/1689 ,  G11C7/22 ,  G11C11/4093 ,  G11C29/022 ,  G11C29/028 ,  G11C29/10

    Abstract: Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.

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