公开(公告)号：US20250140323A1

公开(公告)日：2025-05-01

申请号：US18781524

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Kishore K. Muchherla ,  Hong Lu ,  Akira Goda ,  Shyam Sunder Raghunathan ,  Peter Feeley ,  Emilio Camerlenghi ,  Paolo Tessariol

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08

Abstract: An apparatus comprises a memory array comprising a plurality of physical blocks of memory cells each comprising more than two erase blocks, with each of the more than two erase blocks of each respective physical block comprising memory cells coupled to a same string of memory cells corresponding to the respective physical block. A controller can operate the memory array in accordance with a logical block implementation in which each logical block comprises: a first erase block adjacent to a first end of a particular string corresponding to a first physical block; and a second erase block. The second erase block is either: located in the first physical block and not adjacent to a second end of the particular string corresponding to the first physical block; or located in a second physical block and adjacent to a first end of a particular string corresponding to the second physical block.

公开(公告)号：US20250133751A1

公开(公告)日：2025-04-24

申请号：US19007195

申请日：2024-12-31

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Paolo Tessariol ,  Enrico Varesi ,  Lorenzo Fratin

IPC: G11C8/14 ,  H10B63/10

Abstract: Techniques for electronic memory are described. A method for forming a memory array may include forming memory cells, a dielectric material between word lines, and a sealing material on sidewalls of the dielectric material. The method may also include removing at least a portion of the sealing material to expose the dielectric material. Also, the method may include forming one or more voids in the dielectric material, where the one or more voids may separate the word lines from one another. The memory array may include the memory cells, the word lines, pillars, and piers, where the word lines may be separated from one another by the one or more voids to form air gaps.

公开(公告)号：US20250038109A1

公开(公告)日：2025-01-30

申请号：US18916144

申请日：2024-10-15

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Graham R. Wolstenholme ,  Aaron Yip

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/00 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35 ,  H10B43/50

Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

公开(公告)号：US12154825B2

公开(公告)日：2024-11-26

申请号：US17447505

申请日：2021-09-13

Applicant: Micron Technology, Inc.

Inventor： Raja Kumar Varma Manthena ,  Paolo Tessariol

IPC: H10B41/10 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

Abstract: A method of forming a microelectronic device comprises forming a stack structure over a source structure, forming pillar structures vertically extending through the stack structure, and forming at least one trench vertically extending through the stack structure. The at least one trench defines at least one stadium structure comprising opposing stair step structures having steps comprising horizontal ends of tiers. Additional trenches may be formed to vertically extend through the stack structure, and at least one further trench may be formed to vertically extend through the stack structure. The at least one further trench defines at least one additional stadium structure comprising additional opposing stair step structures having additional steps comprising additional horizontal ends of the tiers. A dielectric material may be formed within the at least one trench, the additional trenches, and the at least one further trench. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20240081067A1

公开(公告)日：2024-03-07

申请号：US18508875

申请日：2023-11-14

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  Justin B. Dorhout ,  Jian Li ,  Haitao Liu ,  Paolo Tessariol

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.

公开(公告)号：US20240057328A1

公开(公告)日：2024-02-15

申请号：US17819575

申请日：2022-08-12

Applicant: Micron Technology, Inc.

Inventor： Umberto Maria Meotto ,  Anna Maria Conti ,  Paolo Tessariol

IPC: H01L27/11524 ,  H01L27/11582 ,  H01L27/11551

CPC classification number: H01L27/11524 ,  H01L27/11582 ,  H01L27/11551 ,  H01L29/0649

Abstract: A microelectronic device includes a stack structure including tiers each including insulative material and conductive material vertically adjacent the insulative material. The stack structure divided into at least two blocks separated from one another. The microelectronic device further includes at least one slot structure horizontally interposed between the at least two blocks of the stack structure. The at least one slot structure including additional insulative material and at least one contact structure extending through the additional insulative material to source tier underlying the stack structure.

公开(公告)号：US11864387B2

公开(公告)日：2024-01-02

申请号：US18083412

申请日：2022-12-16

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  Justin B. Dorhout ,  Jian Li ,  Haitao Liu ,  Paolo Tessariol

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.

公开(公告)号：US11818902B2

公开(公告)日：2023-11-14

申请号：US17497461

申请日：2021-10-08

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Corrado Villa ,  Paolo Tessariol

IPC: G11C8/08 ,  H10B63/00

CPC classification number: H10B63/84 ,  G11C8/08

Abstract: A vertical 3D memory device may comprise: a substrate including a plurality of conductive contacts each coupled with a respective one of a plurality of digit lines; a plurality of word line plates separated from one another with respective dielectric layers on the substrate, the plurality of word line plates including at least a first set of word lines separated from at least a second set of word lines with a dielectric material extending in a serpentine shape and at least a third set of word lines separated from at least a fourth set of word lines with a dielectric material extending in a serpentine shape; at least one separation layer separating the first set of word lines and the second set of word lines from the third set of word lines and the fourth set of word lines, wherein the at least one separation layer is parallel to both a digit line and a word line; and a plurality of storage elements each formed in a respective one of a plurality of recesses such that a respective storage element is surrounded by a respective word line, a respective digit line, respective dielectric layers, and a conformal material formed on a sidewall of a word line facing a digit line.

公开(公告)号：US20230317604A1

公开(公告)日：2023-10-05

申请号：US17657264

申请日：2022-03-30

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Harsh Narendrakumar Jain ,  Indra V. Chary ,  Umberto Maria Meotto ,  Paolo Tessariol

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L21/76816 ,  H01L21/76877

Abstract: Microelectronic devices include a stack structure having a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of stadiums, within the stack structure, includes stadiums of differing numbers of staircase sets, such as a stadium having multiple parallel sets of staircases and an additional stadium having a single set of staircases. Each of the staircases comprises steps, at ends of the conductive structures, with a same multi-tier riser height. In methods of fabrication, a same initial stadium opening may be concurrently formed for each of the stadiums—regardless of whether the stadium is to include the single set or the multiple parallel sets of staircases—with the steps of the same multi-tier riser height. Electronic systems are also disclosed.

公开(公告)号：US20230255023A1

公开(公告)日：2023-08-10

申请号：US17665346

申请日：2022-02-04

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Richard J. Hill ,  Yoshiaki Fukuzumi ,  Paolo Tessariol

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  G11C16/0483

Abstract: Memory circuitry comprising strings of memory cells comprising memory blocks individually comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers of the memory blocks extend from the memory-array region into a stair-step region. Individual of the memory blocks in the stair-step region comprise a flight of operative stairs. Individual of the operative stairs comprise one of the conductive tiers. At least some immediately-laterally-adjacent of the individual memory blocks in the stair-step region have their flights of operative stairs laterally-separated by a stack comprising two vertically-alternating different-composition insulative materials. Other embodiments, including method, are disclosed.