公开(公告)号：US11139001B2

公开(公告)日：2021-10-05

申请号：US16882204

申请日：2020-05-22

Applicant: Micron Technology, Inc.

Inventor： Kurt D. Beigel ,  Scott E. Sills

IPC: G11C5/02 ,  H01L21/308 ,  H01L29/786 ,  H01L27/092 ,  H01L27/02 ,  H03K19/0948 ,  H01L21/8238 ,  H01L21/822 ,  H01L29/66 ,  H01L27/06 ,  H01L27/24 ,  G11C7/12 ,  G11C8/10 ,  G11C7/06 ,  G11C8/08 ,  G11C29/44 ,  G11C5/14

Abstract: A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting a gate electrode shared by neighboring vertical transistors thereof. A control logic assembly, a control logic device, an electronic system, a method of forming a control logic device, and a method of operating a semiconductor device are also described.

公开(公告)号：US20210184079A1

公开(公告)日：2021-06-17

申请号：US17175224

申请日：2021-02-12

Applicant: Micron Technology, Inc.

Inventor： Scott D. Schellhammer ,  Scott E. Sills ,  Lifang Xu ,  Thomas Gehrke ,  Zaiyuan Ren ,  Anton J. De Villiers

IPC: H01L33/24 ,  H01L33/00 ,  H01L33/16 ,  H01L33/22 ,  H01L33/32

Abstract: Light emitting diodes and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode (LED) includes a substrate, a semiconductor material carried by the substrate, and an active region proximate to the semiconductor material. The semiconductor material has a first surface proximate to the substrate and a second surface opposite the first surface. The second surface of the semiconductor material is generally non-planar, and the active region generally conforms to the non-planar second surface of the semiconductor material.

公开(公告)号：US20210080095A1

公开(公告)日：2021-03-18

申请号：US17107720

申请日：2020-11-30

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills

IPC: F21V29/67 ,  F21V9/30 ,  F21V29/83 ,  F21V7/00 ,  F21V13/14

Abstract: A solid state lighting (SSL) with a solid state emitter (SSE) having thermally conductive projections extending into an air channel, and methods of making and using such SSLs. The thermally conductive projections can be fins, posts, or other structures configured to transfer heat into a fluid medium, such as air. The projections can be electrical contacts between the SSE and a power source. The air channel can be oriented generally vertically such that air in the channel warmed by the SSE flows upward through the channel.

公开(公告)号：US20210050346A1

公开(公告)日：2021-02-18

申请号：US17089374

申请日：2020-11-04

Applicant: Micron Technology, Inc.

Inventor： Kurt D. Beigel ,  Scott E. Sills

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/822 ,  H01L21/8238 ,  G11C29/44 ,  G11C5/02 ,  G11C29/14 ,  G11C29/12 ,  G11C7/10 ,  H01L29/66 ,  H01L27/105 ,  G11C29/00 ,  G11C29/42

Abstract: A semiconductor device includes a stack structure comprising decks. Each deck of the stack structure comprises a memory element level comprising memory elements and control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region or the N-type channel region overlying the first subdeck structure. Related semiconductor devices and methods of forming the semiconductor devices are disclosed.

公开(公告)号：US10910255B2

公开(公告)日：2021-02-02

申请号：US16789368

申请日：2020-02-12

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills

IPC: H01L27/24 ,  H01L21/762 ,  G11C8/12 ,  H01L27/11502 ,  H01L21/8239 ,  H01L27/10 ,  H01L27/11585 ,  G11C11/22 ,  H01L27/102

Abstract: Some embodiments include a memory array having a first set of lines extending along a first direction, and a second set of lines over the first set of lines and extending along a second direction. Lines of the second set cross lines of the first set at cross-point locations. Memory structures are within the cross-point locations. Each memory structure includes a top electrode material, a bottom electrode material and a programmable material. Rails of insulative material extend parallel to the lines of the second set and alternate with the lines of the second set along the first direction. The programmable material has first regions within the memory structures and second regions over the rails of insulative material. A planarized surface extends across the lines of the second set and across the second regions of the programmable material. Some embodiments include methods of forming memory arrays.

公开(公告)号：US20200312840A1

公开(公告)日：2020-10-01

申请号：US16902752

申请日：2020-06-16

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Kurt D. Beigel

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L27/092 ,  H01L27/12 ,  G11C5/02 ,  H01L27/105 ,  G11C29/42 ,  H01L27/24 ,  G11C29/00

Abstract: A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting transistors laterally displaced from one another. A memory device, a thin film transistor control logic assembly, an electronic system, and a method of operating a semiconductor device are also described.

公开(公告)号：US20200185265A1

公开(公告)日：2020-06-11

申请号：US16789368

申请日：2020-02-12

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills

IPC: H01L21/762 ,  H01L27/24 ,  H01L27/11585 ,  H01L27/10 ,  H01L21/8239 ,  H01L27/11502 ,  G11C8/12

Abstract: Some embodiments include a memory array having a first set of lines extending along a first direction, and a second set of lines over the first set of lines and extending along a second direction. Lines of the second set cross lines of the first set at cross-point locations. Memory structures are within the cross-point locations. Each memory structure includes a top electrode material, a bottom electrode material and a programmable material. Rails of insulative material extend parallel to the lines of the second set and alternate with the lines of the second set along the first direction. The programmable material has first regions within the memory structures and second regions over the rails of insulative material. A planarized surface extends across the lines of the second set and across the second regions of the programmable material. Some embodiments include methods of forming memory arrays.

公开(公告)号：US20200161434A1

公开(公告)日：2020-05-21

申请号：US16688854

申请日：2019-11-19

Applicant: Micron Technology, Inc.

Inventor： Yi Fang Lee ,  Isamu Asano ,  Ramanathan Gandhi ,  Scott E. Sills

IPC: H01L29/22 ,  H01L27/108 ,  G11C11/402 ,  H01L29/786

Abstract: Some embodiments include an integrated assembly having a gate material, an insulative material adjacent the gate material, and a semiconductor oxide adjacent the insulative material. The semiconductor oxide has a channel region proximate the gate material and spaced from the gate material by the insulative material. An electric field along the gate material induces carrier flow within the channel region, with the carrier flow being along a first direction. The semiconductor oxide includes a grain boundary having a portion which extends along a second direction that crosses the first direction of the carrier flow. In some embodiments, the semiconductor oxide has a grain boundary which extends along the first direction and which is offset from the insulative material by an intervening portion of the semiconductor oxide. The carrier flow is within the intervening region and substantially parallel to the grain boundary. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10431629B2

公开(公告)日：2019-10-01

申请号：US15987613

申请日：2018-05-23

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L45/00 ,  H01L27/24 ,  H01L27/10 ,  H01L27/105 ,  H01L27/088

Abstract: A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20190206861A1

公开(公告)日：2019-07-04

申请号：US15858128

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Kurt D. Beigel ,  Scott E. Sills

IPC: H01L27/06 ,  H01L27/105 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/822 ,  H01L21/8238 ,  G11C29/44 ,  G11C5/02 ,  G11C29/14 ,  G11C29/12 ,  G11C7/10 ,  H01L29/66

CPC classification number: H01L27/0688 ,  G11C5/025 ,  G11C5/145 ,  G11C5/147 ,  G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C29/1201 ,  G11C29/14 ,  G11C29/44 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/1052 ,  H01L29/0642 ,  H01L29/42392 ,  H01L29/6675 ,  H01L29/78642 ,  H01L29/78696 ,  H03K19/0948 ,  H03K19/20

Abstract: A semiconductor device includes a stack structure comprising decks. Each deck of the stack structure comprises a memory element level comprising memory elements and control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region or the N-type channel region overlying the first subdeck structure. Related semiconductor devices and methods of forming the semiconductor devices are disclosed.