公开(公告)号：US20070052031A1

公开(公告)日：2007-03-08

申请号：US11404075

申请日：2006-04-14

申请人： Atsuhiro Kinoshita

发明人： Atsuhiro Kinoshita

IPC分类号： H01L23/62

CPC分类号： H01L27/0251 ,  H01L29/665 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： It is made possible to easily set a protection voltage even when a semiconductor device to be protected includes a gate insulating film having a low dielectric breakdown voltage. A semiconductor device includes: a MOS transistor including a first gate insulating film provided on a first element region of first conductivity-type in a semiconductor, a first gate electrode provided on the first gate insulating film, and first impurity regions of second conductivity-type provided in the first element region on both sides of the first gate electrode; and an ESD protection element including a second gate insulating film provided on a second element region of first conductivity-type in the semiconductor substrate and having substantially the same thickness as the first gate insulating film, a second gate electrode provided on the second gate insulating film and connected to the first gate electrode, and second impurity regions of second conductivity-type provided in the second element region on both sides of the second gate electrode.

摘要翻译： 即使要被保护的半导体器件包括具有低介电击穿电压的栅极绝缘膜，也可以容易地设定保护电压。 半导体器件包括：MOS晶体管，包括设置在半导体中的第一导电类型的第一元件区域上的第一栅极绝缘膜，设置在第一栅极绝缘膜上的第一栅极电极和第二导电类型的第一杂质区域 设置在所述第一栅电极的两侧的所述第一元件区域中; 以及ESD保护元件，包括设置在半导体衬底中的第一导电类型的第二元件区上并具有与第一栅极绝缘膜基本相同的厚度的第二栅极绝缘膜，设置在第二栅极绝缘膜上的第二栅电极 并且连接到第一栅电极，以及设置在第二栅电极两侧的第二元件区中的第二导电类型的第二杂质区。

公开(公告)号：US20060220131A1

公开(公告)日：2006-10-05

申请号：US11384269

申请日：2006-03-21

申请人： Atsuhiro Kinoshita ,  Junji Koga ,  Yukio Nakabayashi

发明人： Atsuhiro Kinoshita ,  Junji Koga ,  Yukio Nakabayashi

IPC分类号： H01L21/8234 ,  H01L27/12 ,  H01L21/336 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L27/088 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618

摘要： It is possible to reliably implant an impurity into an impurity forming region, and to form a self-aligned silicides on the entire portion of the source and drain regions. There are provided: a first semiconductor layer of a first conductivity type in a substantially a rectangular solid shape formed on a substrate; a gate electrode formed on a pair of first side portions of the first semiconductor layer facing to each other with a gate insulating film being placed between the gate electrode and the first side portions; a second semiconductor layer of the first conductivity type connected to bottom portions of a pair of second side portions of the first semiconductor layer placed in a substantially perpendicular direction with respect to the first side portions, the second semiconductor layer extending along the substantially perpendicular direction; a first impurity region of a second conductivity type formed in the second semiconductor layer; second impurity regions formed on the pair of side portions of the first semiconductor layer and connected to the first impurity region; and a channel region formed between the second impurity regions of the first semiconductor layer.

公开(公告)号：US09262500B2

公开(公告)日：2016-02-16

申请号：US13569542

申请日：2012-08-08

申请人： Atsuhiro Kinoshita ,  Takao Marukame ,  Kosuke Tatsumura

发明人： Atsuhiro Kinoshita ,  Takao Marukame ,  Kosuke Tatsumura

IPC分类号： G06F17/30 ,  G06F12/02

CPC分类号： G06F17/30587 ,  G06F12/0292

摘要： According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes a first memory, a control circuit and a second memory. The first memory is configured to contain a data area for storing data, and a table area containing the key-value data. The control circuit is configured to perform write and read to the first memory by addressing, and execute a request based on the key-value store. The second memory is configured to store the key-value data in accordance with an instruction from the control circuit. The control circuit performs a set operation by using the key-value data stored in the first memory, and the key-value data stored in the second memory.

摘要翻译： 根据一个实施例，包括包含键值数据作为一对键和与该键对应的值的键值存储器的存储器系统包括第一存储器，控制电路和第二存储器。 第一存储器被配置为包含用于存储数据的数据区域和包含键值数据的表区域。 控制电路被配置为通过寻址来执行对第一存储器的写入和读取，并且基于键值存储执行请求。 第二存储器被配置为根据来自控制电路的指令存储键值数据。 控制电路通过使用存储在第一存储器中的键值数据和存储在第二存储器中的键值数据来执行设置操作。

公开(公告)号：US08653560B2

公开(公告)日：2014-02-18

申请号：US13344107

申请日：2012-01-05

申请人： Kosuke Tatsumura ,  Atsuhiro Kinoshita

发明人： Kosuke Tatsumura ,  Atsuhiro Kinoshita

IPC分类号： H01L29/66

CPC分类号： H01L29/66742 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78684

摘要： According to one embodiment, a fabrication method of a semiconductor device comprising forming a dummy gate with a gate length direction set to a [111] direction perpendicular to a [110] direction on a surface of a supporting substrate having Si1-xGex (0≦x

摘要翻译： 根据一个实施例，一种半导体器件的制造方法，包括在具有Si1-xGex（0 @）的支撑衬底的表面上形成栅极长度方向设置为垂直于[110]方向的[111]方向的虚拟栅极 x <0.5），具有垂直于在表面上设置为[110]方向的表面的晶体取向，形成源极/漏极区域并在虚拟栅极的侧部分上形成绝缘膜。 接下来，使用绝缘膜作为掩模蚀刻伪栅极，并且进一步蚀刻在源极/漏极区域之间的衬底的表面部分。 接下来，通过使用源极/漏极区域的边缘部分作为晶种，在源极/漏极区域之间生长由III-V族半导体或Ge形成的沟道区域。 然后，通过栅极绝缘膜在沟道区的上方形成栅电极。

公开(公告)号：US20130307054A1

公开(公告)日：2013-11-21

申请号：US13606292

申请日：2012-09-07

申请人： Shinichi YASUDA ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Koichiro Zaitsu ,  Masato Oda ,  Atsuhiro Kinoshita ,  Daisuke Hagishima ,  Yoshifumi Nishi ,  Takahiro Kurita ,  Shinobu Fujita

发明人： Shinichi YASUDA ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Koichiro Zaitsu ,  Masato Oda ,  Atsuhiro Kinoshita ,  Daisuke Hagishima ,  Yoshifumi Nishi ,  Takahiro Kurita ,  Shinobu Fujita

IPC分类号： H01L27/105

CPC分类号： G11C16/10 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/7881 ,  H01L29/792

摘要： One embodiment provides a semiconductor integrated circuit, including: a substrate; a plurality of nonvolatile memory portions formed in the substrate, each including a first nonvolatile memory and a second nonvolatile memory; and a plurality of logic transistor portions formed in the substrate, each including at least one of logic transistor, wherein the logic transistors include: a first transistor which is directly connected to drains of the first and second nonvolatile memories at its gate; and a second transistor which is not directly connected to the drains of the first and second nonvolatile memories, and wherein a bottom surface of the gate of each of the logic transistors sandwiching the first and second nonvolatile memories is lower in height from a top surface of the substrate than a bottom surface of the control gate of each of the first and second nonvolatile memories.

摘要翻译： 一个实施例提供一种半导体集成电路，包括：基板; 形成在所述基板中的多个非易失性存储部，每个包括第一非易失性存储器和第二非易失性存储器; 以及形成在所述衬底中的多个逻辑晶体管部分，每个逻辑晶体管部分包括逻辑晶体管中的至少一个，其中所述逻辑晶体管包括：第一晶体管，其第一和第二非易失性存储器的栅极直接连接到第一晶体管; 以及第二晶体管，其不直接连接到第一和第二非易失性存储器的漏极，并且其中夹着第一和第二非易失性存储器的每个逻辑晶体管的栅极的底表面的高度与 所述基板比所述第一和第二非易失性存储器中的每一个的所述控制栅极的底表面。

公开(公告)号：US20130254240A1

公开(公告)日：2013-09-26

申请号：US13729633

申请日：2012-12-28

申请人： Takahiro KURITA ,  Takao Marukame ,  Atsuhiro Kinoshita

发明人： Takahiro KURITA ,  Takao Marukame ,  Atsuhiro Kinoshita

IPC分类号： G06F17/30

CPC分类号： G06F16/21 ,  G06F16/278

摘要： According to an embodiment, a method of processing a database includes dividing a first data table that includes records including data in a plurality of columns into a plurality of second data tables based on a predetermined criterion for dividing columns. Each of the second data tables includes data in at least one column. The method also includes dividing each of the second data tables into a plurality of third data tables based on a predetermined criterion for dividing data in units of a record based on the data. Each of the third data tables includes at least one record. The method also includes storing the third data tables in a plurality of storage units, respectively. Each of the storage units allows the data to be read independently.

摘要翻译： 根据实施例，处理数据库的方法包括：基于用于划分列的预定标准，将包括多列中的数据的记录划分成多个第二数据表的第一数据表。 每个第二数据表包括至少一列中的数据。 该方法还包括基于用于基于数据以记录为单位划分数据的预定标准，将每个第二数据表分成多个第三数据表。 每个第三数据表包括至少一个记录。 该方法还包括分别将第三数据表存储在多个存储单元中。 每个存储单元允许独立地读取数据。

公开(公告)号：US08525251B2

公开(公告)日：2013-09-03

申请号：US13221292

申请日：2011-08-30

申请人： Daisuke Hagishima ,  Atsuhiro Kinoshita ,  Kazuya Matsuzawa ,  Kazutaka Ikegami ,  Yoshifumi Nishi

发明人： Daisuke Hagishima ,  Atsuhiro Kinoshita ,  Kazuya Matsuzawa ,  Kazutaka Ikegami ,  Yoshifumi Nishi

IPC分类号： H01L29/792

CPC分类号： H01L29/7881 ,  G11C16/0408 ,  H01L27/1052 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11807 ,  H01L29/66825

摘要： A nonvolatile programmable logic switch according to an embodiment includes: a memory cell transistor including: a first source region and a first drain region of a second conductivity type formed at a distance from each other in a first semiconductor region of a first conductivity type; a first insulating film, a charge storage film, a second insulating film, and a control gate stacked in this order and formed on the first semiconductor region between the first source region and the first drain region; a pass transistor including: a second source region and a second drain region of a second conductivity type formed at a distance from each other in a second semiconductor region of the first conductivity type; a third insulating film, a gate electrode stacked in this order and formed on the second semiconductor region between the second source region and the second drain region, the gate electrode being electrically connected to the first drain region; and an electrode for applying a substrate bias to the first and second semiconductor regions.

摘要翻译： 根据实施例的非易失性可编程逻辑开关包括：存储单元晶体管，包括：在第一导电类型的第一半导体区域中彼此间隔开形成的第二导电类型的第一源极区域和第一漏极区域; 第一绝缘膜，电荷存储膜，第二绝缘膜和控制栅极，并且形成在第一源极区域和第一漏极区域之间的第一半导体区域上; 传输晶体管，包括：在第一导电类型的第二半导体区域中彼此成一定距离地形成的第二导电类型的第二源极区域和第二漏极区域; 第三绝缘膜，栅极电极，并且形成在第二源极区域和第二漏极区域之间的第二半导体区域上，栅极电连接到第一漏极区域; 以及用于将衬底偏压施加到第一和第二半导体区域的电极。

公开(公告)号：US20130015519A1

公开(公告)日：2013-01-17

申请号：US13622612

申请日：2012-09-19

申请人： Shosuke Fujii ,  Kiwamu Sakuma ,  Jun Fujiki ,  Atsuhiro Kinoshita

发明人： Shosuke Fujii ,  Kiwamu Sakuma ,  Jun Fujiki ,  Atsuhiro Kinoshita

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L27/11551 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11578

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes first to n-th semiconductor layers which are stacked in a first direction perpendicular to a surface of a semiconductor substrate and which extend in a second direction parallel to the surface of the semiconductor substrate, an electrode which extends in the first direction along side surfaces of the first to n-th semiconductor layers, the side surfaces of the first to n-th semiconductor layers exposing in a third direction perpendicular to the first and second directions, and first to n-th charge storage layers located between the first to n-th semiconductor layers and the electrode respectively. The first to n-th charge storage layers are separated from each other in areas between the first to n-th semiconductor layers.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一至第n半导体层，它们沿垂直于半导体衬底的表面的第一方向堆叠并且沿与半导体衬底的表面平行的第二方向延伸， 电极，其沿第一方向沿着第一至第n半导体层的侧表面延伸，第一至第n半导体层的侧表面在垂直于第一和第二方向的第三方向上暴露，以及第一至第n- 分别位于第一至第n半导体层之间的电荷存储层和电极。 第一至第n电荷存储层在第一至第n半导体层之间的区域中彼此分离。

公开(公告)号：US08343870B2

公开(公告)日：2013-01-01

申请号：US12585034

申请日：2009-09-01

申请人： Atsuhiro Kinoshita ,  Junji Koga

发明人： Atsuhiro Kinoshita ,  Junji Koga

IPC分类号： H01L21/44

CPC分类号： H01L29/6659 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6653

摘要： A semiconductor device which can effectively suppress a short channel effect and junction leakage is provided. A semiconductor device includes a field effect transistor. The field effect transistor includes a first semiconductor region of a first conductivity type, a gate electrode formed on a gate insulating film, and source and drain electrodes. The field effect transistor also includes second semiconductor regions of a second conductivity type. The field effect transistor further includes third semiconductor regions of the second conductivity type having an impurity concentration higher than that of the second semiconductor region and formed between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions, and side wall insulating films formed on both the side surfaces of the gate electrode. The source electrode and the drain electrode are separated from the side wall insulating films.

公开(公告)号：US20110246451A1

公开(公告)日：2011-10-06

申请号：US12888897

申请日：2010-09-23

申请人： Kosuke Tatsumura ,  Atsuhiro Kinoshita

发明人： Kosuke Tatsumura ,  Atsuhiro Kinoshita

IPC分类号： G06F17/30

CPC分类号： G06F17/30106 ,  G06F17/30109

摘要： According to one embodiment, a storage device includes an interface, a first and second memory blocks and a controller. The interface receives a content search request. The first memory block stores files and inverted files corresponding to contents included in the files. The second memory block stores a file search table. The controller creates the inverted file for each content included in the files and stores IDs of the files including the content in the inverted file. The controller obtains, by search of the content, a corresponding inverted file from the inverted files stored in the first memory block and stores, in the file search table, the IDs of the files included in the obtained inverted file. The controller outputs the IDs of the files stored in the file search table from the interface as a search result for the content search request.

摘要翻译： 根据一个实施例，存储设备包括接口，第一和第二存储器块以及控制器。 接口接收内容搜索请求。 第一个存储块存储与文件中包含的内容相对应的文件和反转文件。 第二存储器块存储文件搜索表。 控制器为包含在文件中的每个内容创建反转文件，并将包含内容的文件的ID存储在反转文件中。 控制器通过搜索内容，从存储在第一存储器块中的反转文件中获得相应的反转文件，并在文件搜索表中存储所获得的反转文件中包括的文件的ID。 控制器从接口输出存储在文件搜索表中的文件的ID作为内容搜索请求的搜索结果。