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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09007823B2

    公开(公告)日：2015-04-14

    申请号：US13480853

    申请日：2012-05-25

    申请人： Takahiro Kurita ,  Yoshifumi Nishi ,  Kosuke Tatsumura ,  Atsuhiro Kinoshita

    发明人： Takahiro Kurita ,  Yoshifumi Nishi ,  Kosuke Tatsumura ,  Atsuhiro Kinoshita

    IPC分类号： G11C11/34 ,  H01L21/28 ,  G11C7/02 ,  G11C11/403 ,  H01L29/423 ,  H01L29/51 ,  H01L27/108

    CPC分类号： H01L21/28291 ,  G11C7/02 ,  G11C11/403 ,  H01L21/28282 ,  H01L27/108 ,  H01L27/10873 ,  H01L29/4234 ,  H01L29/516

    摘要： A semiconductor device according to an embodiment includes: a first transistor including a gate connected to a first interconnection, a first source, and a first drain, one of the first source and the first drain being connected to a second interconnection; and a second transistor including a gate structure, a second source, and a second drain, one of the second source and second drain being connected to a third interconnection and the other of the second source and second drain being connected to a fourth interconnection. The gate structure includes a gate insulation film, a gate electrode, and a threshold-modulating film provided between the gate insulation film and the gate electrode to modulate a threshold voltage, the other of the first source and first drain of the first transistor is connected to the gate electrode.

    摘要翻译： 根据实施例的半导体器件包括：第一晶体管，包括连接到第一互连的栅极，第一源极和第一漏极，第一源极和第一漏极中的一个连接到第二互连; 以及第二晶体管，其包括栅极结构，第二源极和第二漏极，所述第二源极和第二漏极中的一个连接到第三互连，并且所述第二源极和第二漏极中的另一个连接到第四互连。 栅极结构包括栅极绝缘膜，栅极电极和设置在栅极绝缘膜和栅电极之间以调节阈值电压的阈值调制膜，第一晶体管的第一源极和第一漏极中的另一个被连接 到栅电极。

    Method for controlling motorized storing door mirror
    2.
    发明授权
    Method for controlling motorized storing door mirror 失效
    用于控制电动存储门镜的方法

    公开(公告)号：US06838850B2

    公开(公告)日：2005-01-04

    申请号：US10220297

    申请日：2002-01-11

    申请人： Takahiro Kurita ,  Mitsuyoshi Nagao

    发明人： Takahiro Kurita ,  Mitsuyoshi Nagao

    IPC分类号： B60R1/07 ,  B60R1/074 ,  G05B5/00

    CPC分类号： B60R1/074 ,  B60R1/07

    摘要： A control unit for an electrically retractable door mirror includes a motor to drive rotationally a door mirror to a stored position or a normal position, a change-over switch, and first and second control circuits. The first and second control circuits include electronic switches respectively that are capable of switching on/off depending on the polarity of an electrical signal switched by the change-over switch. Excess current detecting devices, whose electrical resistances grow with an increase in a current, are connected to the electronic switches in series respectively. And, shutoff switches switch off the electronic switches respectively when a voltage generated in the excess current detecting devices exceeds a predetermined value.

    摘要翻译： 用于电气可伸缩门镜的控制单元包括电动机，用于将门镜旋转地驱动到存储位置或正常位置，转换开关以及第一和第二控制电路。 第一控制电路和第二控制电路分别包括能够根据由转换开关切换的电信号的极性来接通/断开的电子开关。 电流随着电流增加而增大的过电流检测装置分别连接到电子开关。 并且，当过电流检测装置中产生的电压超过预定值时，截止开关分别关断电子开关。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    4.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
    半导体集成电路

    公开(公告)号：US20130307054A1

    公开(公告)日：2013-11-21

    申请号：US13606292

    申请日：2012-09-07

    申请人： Shinichi YASUDA ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Koichiro Zaitsu ,  Masato Oda ,  Atsuhiro Kinoshita ,  Daisuke Hagishima ,  Yoshifumi Nishi ,  Takahiro Kurita ,  Shinobu Fujita

    发明人： Shinichi YASUDA ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Koichiro Zaitsu ,  Masato Oda ,  Atsuhiro Kinoshita ,  Daisuke Hagishima ,  Yoshifumi Nishi ,  Takahiro Kurita ,  Shinobu Fujita

    IPC分类号： H01L27/105

    CPC分类号： G11C16/10 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/7881 ,  H01L29/792

    摘要： One embodiment provides a semiconductor integrated circuit, including: a substrate; a plurality of nonvolatile memory portions formed in the substrate, each including a first nonvolatile memory and a second nonvolatile memory; and a plurality of logic transistor portions formed in the substrate, each including at least one of logic transistor, wherein the logic transistors include: a first transistor which is directly connected to drains of the first and second nonvolatile memories at its gate; and a second transistor which is not directly connected to the drains of the first and second nonvolatile memories, and wherein a bottom surface of the gate of each of the logic transistors sandwiching the first and second nonvolatile memories is lower in height from a top surface of the substrate than a bottom surface of the control gate of each of the first and second nonvolatile memories.

    摘要翻译： 一个实施例提供一种半导体集成电路，包括：基板; 形成在所述基板中的多个非易失性存储部，每个包括第一非易失性存储器和第二非易失性存储器; 以及形成在所述衬底中的多个逻辑晶体管部分，每个逻辑晶体管部分包括逻辑晶体管中的至少一个，其中所述逻辑晶体管包括：第一晶体管，其第一和第二非易失性存储器的栅极直接连接到第一晶体管; 以及第二晶体管，其不直接连接到第一和第二非易失性存储器的漏极，并且其中夹着第一和第二非易失性存储器的每个逻辑晶体管的栅极的底表面的高度与 所述基板比所述第一和第二非易失性存储器中的每一个的所述控制栅极的底表面。

    METHOD OF PROCESSING DATABASE, DATABASE PROCESSING APPARATUS, COMPUTER PROGRAM PRODUCT
    5.
    发明申请
    METHOD OF PROCESSING DATABASE, DATABASE PROCESSING APPARATUS, COMPUTER PROGRAM PRODUCT 审中-公开
    数据库处理方法，数据库处理设备，计算机程序产品

    公开(公告)号：US20130254240A1

    公开(公告)日：2013-09-26

    申请号：US13729633

    申请日：2012-12-28

    申请人： Takahiro KURITA ,  Takao Marukame ,  Atsuhiro Kinoshita

    发明人： Takahiro KURITA ,  Takao Marukame ,  Atsuhiro Kinoshita

    IPC分类号： G06F17/30

    CPC分类号： G06F16/21 ,  G06F16/278

    摘要： According to an embodiment, a method of processing a database includes dividing a first data table that includes records including data in a plurality of columns into a plurality of second data tables based on a predetermined criterion for dividing columns. Each of the second data tables includes data in at least one column. The method also includes dividing each of the second data tables into a plurality of third data tables based on a predetermined criterion for dividing data in units of a record based on the data. Each of the third data tables includes at least one record. The method also includes storing the third data tables in a plurality of storage units, respectively. Each of the storage units allows the data to be read independently.

    摘要翻译： 根据实施例，处理数据库的方法包括：基于用于划分列的预定标准，将包括多列中的数据的记录划分成多个第二数据表的第一数据表。 每个第二数据表包括至少一列中的数据。 该方法还包括基于用于基于数据以记录为单位划分数据的预定标准，将每个第二数据表分成多个第三数据表。 每个第三数据表包括至少一个记录。 该方法还包括分别将第三数据表存储在多个存储单元中。 每个存储单元允许独立地读取数据。

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20130077397A1

    公开(公告)日：2013-03-28

    申请号：US13480853

    申请日：2012-05-25

    申请人： Takahiro KURITA ,  Yoshifumi NISHI ,  Kosuke TATSUMURA ,  Atsuhiro KINOSHITA

    发明人： Takahiro KURITA ,  Yoshifumi NISHI ,  Kosuke TATSUMURA ,  Atsuhiro KINOSHITA

    IPC分类号： H01L27/105 ,  G11C11/40

    CPC分类号： H01L21/28291 ,  G11C7/02 ,  G11C11/403 ,  H01L21/28282 ,  H01L27/108 ,  H01L27/10873 ,  H01L29/4234 ,  H01L29/516

    摘要： A semiconductor device according to an embodiment includes: a first transistor including a gate connected to a first interconnection, a first source, and a first drain, one of the first source and the first drain being connected to a second interconnection; and a second transistor including a gate structure, a second source, and a second drain, one of the second source and second drain being connected to a third interconnection and the other of the second source and second drain being connected to a fourth interconnection. The gate structure includes a gate insulation film, a gate electrode, and a threshold-modulating film provided between the gate insulation film and the gate electrode to modulate a threshold voltage, the other of the first source and first drain of the first transistor is connected to the gate electrode.

    摘要翻译： 根据实施例的半导体器件包括：第一晶体管，包括连接到第一互连的栅极，第一源极和第一漏极，第一源极和第一漏极中的一个连接到第二互连; 以及第二晶体管，其包括栅极结构，第二源极和第二漏极，所述第二源极和第二漏极中的一个连接到第三互连，并且所述第二源极和第二漏极中的另一个连接到第四互连。 栅极结构包括栅极绝缘膜，栅极电极和设置在栅极绝缘膜和栅电极之间以调节阈值电压的阈值调制膜，第一晶体管的第一源极和第一漏极中的另一个被连接 到栅电极。

    NONVOLATILE PROGRAMMABLE LOGIC SWITCH
    7.
    发明申请
    NONVOLATILE PROGRAMMABLE LOGIC SWITCH 有权
    非易失性可编程逻辑开关

    公开(公告)号：US20120243336A1

    公开(公告)日：2012-09-27

    申请号：US13240087

    申请日：2011-09-22

    申请人： Yoshifumi NISHI ,  Daisuke HAGISHIMA ,  Shinichi YASUDA ,  Tetsufumi TANAMOTO ,  Takahiro KURITA ,  Atsuhiro KINOSHITA ,  Shinobu FUJITA

    发明人： Yoshifumi NISHI ,  Daisuke HAGISHIMA ,  Shinichi YASUDA ,  Tetsufumi TANAMOTO ,  Takahiro KURITA ,  Atsuhiro KINOSHITA ,  Shinobu FUJITA

    IPC分类号： G11C16/10 ,  H01L29/792

    CPC分类号： H01L27/11568 ,  G11C16/0458 ,  G11C16/10 ,  H01L27/11573 ,  H01L27/11803

    摘要： An aspect of the present embodiment, there is provided a nonvolatile programmable logic switch including a first memory cell transistor, a second memory cell transistor, a pass transistor and a first substrate electrode applying a substrate voltage to the pass transistor, wherein a writing voltage is applied to the first wiring, a first voltage is applied to one of a second wiring and a third wiring and a second voltage which is lower than the first voltage is applied to the other of the second wiring and the third wiring, and the first substrate voltage which is higher than the second voltage and lower than the first voltage is applied to a well of the pass transistor, when data is written into the first memory cell transistor or the second memory cell transistor.

    摘要翻译： 本实施例的一个方面提供了一种非易失性可编程逻辑开关，包括第一存储单元晶体管，第二存储单元晶体管，传输晶体管和向该通过晶体管施加衬底电压的第一衬底电极，其中写入电压为 施加到第一布线，第一电压施加到第二布线和第三布线中的一个，并且低于第一电压的第二电压施加到第二布线和第三布线中的另一布线，第一基板 当数据被写入第一存储单元晶体管或第二存储单元晶体管时，高于第二电压并低于第一电压的电压被施加到传输晶体管的阱。

    Nonvolatile programmable logic switch
    9.
    发明授权
    Nonvolatile programmable logic switch 有权
    非易失性可编程逻辑开关

    公开(公告)号：US08553464B2

    公开(公告)日：2013-10-08

    申请号：US13240087

    申请日：2011-09-22

    申请人： Yoshifumi Nishi ,  Daisuke Hagishima ,  Shinichi Yasuda ,  Tetsufumi Tanamoto ,  Takahiro Kurita ,  Atsuhiro Kinoshita ,  Shinobu Fujita

    发明人： Yoshifumi Nishi ,  Daisuke Hagishima ,  Shinichi Yasuda ,  Tetsufumi Tanamoto ,  Takahiro Kurita ,  Atsuhiro Kinoshita ,  Shinobu Fujita

    IPC分类号： G11C11/35

    CPC分类号： H01L27/11568 ,  G11C16/0458 ,  G11C16/10 ,  H01L27/11573 ,  H01L27/11803

    摘要： An aspect of the present embodiment, there is provided a nonvolatile programmable logic switch including a first memory cell transistor, a second memory cell transistor, a pass transistor and a first substrate electrode applying a substrate voltage to the pass transistor, wherein a writing voltage is applied to the first wiring, a first voltage is applied to one of a second wiring and a third wiring and a second voltage which is lower than the first voltage is applied to the other of the second wiring and the third wiring, and the first substrate voltage which is higher than the second voltage and lower than the first voltage is applied to a well of the pass transistor, when data is written into the first memory cell transistor or the second memory cell transistor.

    摘要翻译： 本实施例的一个方面提供了一种非易失性可编程逻辑开关，包括第一存储单元晶体管，第二存储单元晶体管，传输晶体管和向该通过晶体管施加衬底电压的第一衬底电极，其中写入电压为 施加到第一布线，第一电压施加到第二布线和第三布线中的一个，并且低于第一电压的第二电压施加到第二布线和第三布线中的另一布线，第一基板 当数据被写入第一存储单元晶体管或第二存储单元晶体管时，高于第二电压并低于第一电压的电压被施加到传输晶体管的阱。