公开(公告)号：US20210296192A1

公开(公告)日：2021-09-23

申请号：US16821536

申请日：2020-03-17

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L23/29 ,  H01L23/053

Abstract: This patent application relates to methods and apparatus for temperature modification within a stack of microelectronic devices for mutual collective bonding of the microelectronic devices, and to related substrates and assemblies.

公开(公告)号：US20210272846A1

公开(公告)日：2021-09-02

申请号：US16994941

申请日：2020-08-17

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L21/78 ,  H01L21/56 ,  H01L21/02 ,  H01L21/683 ,  H01L21/268

Abstract: Singulated integrated circuit (IC) dice are provided. The singulated IC dice are positioned on dicing tape to provide open space between sides of adjacent singulated IC dice. An underfill layer and a protective cover film is disposed above the singulated IC dice and the open space between the sides of the adjacent singulated IC dice. The underfill layer and the protective cover film include one or more photodefinable materials. An exposure operation is performed to produce a pattern on the underfill layer and the protective cover film. Based on the pattern, the underfill layer and the protective cover film is removed at areas above the open space between the sides of the adjacent singulated IC dice to create portions of the underfill layer and portions of the protective cover film that are disposed above the singulated IC dice.

公开(公告)号：US20210193606A1

公开(公告)日：2021-06-24

申请号：US17198144

申请日：2021-03-10

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Benjamin L. McClain

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor device assembly is provided. The assembly includes a first package element and a second package element disposed over the first package element. The assembly further includes a plurality of die support structures between the first and second package elements, wherein each of the plurality of die support structures has a first height, a lower portion surface-mounted to the first package element and an upper portion in contact with the second package element. The assembly further includes a plurality of interconnects between the first and second package elements, wherein each of the plurality of interconnects includes a conductive pillar having a second height, a conductive pad, and a bond material with a solder joint thickness between the conductive pillar and the conductive pad. The first height is about equal to a sum of the solder joint thickness and the second height.

公开(公告)号：US10950568B2

公开(公告)日：2021-03-16

申请号：US15603327

申请日：2017-05-23

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Benjamin L. McClain

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L25/16 ,  H01L25/18

Abstract: A semiconductor device assembly is provided. The assembly includes a first package element and a second package element disposed over the first package element. The assembly further includes a plurality of die support structures between the first and second package elements, wherein each of the plurality of die support structures has a first height, a lower portion surface-mounted to the first package element and an upper portion in contact with the second package element. The assembly further includes a plurality of interconnects between the first and second package elements, wherein each of the plurality of interconnects includes a conductive pillar having a second height, a conductive pad, and a bond material with a solder joint thickness between the conductive pillar and the conductive pad. The first height is about equal to a sum of the solder joint thickness and the second height.

公开(公告)号：US10276539B1

公开(公告)日：2019-04-30

申请号：US15797900

申请日：2017-10-30

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Benjamin L. McClain ,  C. Alexander Ernst ,  Jeremy E. Minnich

IPC: H01L23/00

Abstract: A semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a pillar. The semiconductor device assembly includes a semiconductor device disposed over another semiconductor device. At least one pillar extends from one semiconductor device towards a pad on the other semiconductor device. The barrier on the exterior of the pillar may be a standoff to control a bond line between the semiconductor devices. The barrier may reduce solder bridging and may prevent reliability and electromigration issues that can result from the IMC formation between the solder and copper portions of a pillar. The barrier may help align the pillar with a pad when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of the semiconductor devices. Windows or slots in the barrier may permit the expansion of solder in predetermined directions while preventing bridging in other directions.

公开(公告)号：US09966347B2

公开(公告)日：2018-05-08

申请号：US15624493

申请日：2017-06-15

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Jaspreet S. Gandhi ,  Christopher J. Gambee ,  Satish Yeldandi

IPC: H01L21/20 ,  H01L21/768 ,  H01L29/43 ,  H01L29/84 ,  H01L23/498 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/038 ,  H01L2224/0382 ,  H01L2224/039 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05583 ,  H01L2224/05584 ,  H01L2224/05687 ,  H01L2224/94 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/365 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/053 ,  H01L2924/054 ,  H01L2224/03

Abstract: The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.

公开(公告)号：US09704781B2

公开(公告)日：2017-07-11

申请号：US14084037

申请日：2013-11-19

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Jaspreet S. Gandhi ,  Christopher J. Gambee ,  Satish Yeldandi

IPC: H01L23/498 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/48 ,  H01L21/44 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/038 ,  H01L2224/0382 ,  H01L2224/039 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05583 ,  H01L2224/05584 ,  H01L2224/05687 ,  H01L2224/94 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/365 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/053 ,  H01L2924/054 ,  H01L2224/03

Abstract: The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.

公开(公告)号：US20150137353A1

公开(公告)日：2015-05-21

申请号：US14084037

申请日：2013-11-19

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Jaspreet S. Gandhi ,  Christopher J. Gambee ,  Satish Yeldandi

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/038 ,  H01L2224/0382 ,  H01L2224/039 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05583 ,  H01L2224/05584 ,  H01L2224/05687 ,  H01L2224/94 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/365 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/053 ,  H01L2924/054 ,  H01L2224/03

Abstract: The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.

Abstract translation: 本技术涉及制造具有用于管芯到管芯和/或封装到封装互连或其它类型互连的具有凸块下金属（UBM）结构的半导体管芯。 在一个实施例中，用于在半导体管芯上形成凸块状凸起的金属（UBM）结构的方法包括通过将第一材料镀在种子结构的第一区域上并在第一材料上沉积第二材料来构造UBM柱。 第一材料具有第一电位，第二材料具有大于第一电位的第二电势。 该方法还包括减小第一材料和第二材料之间的电位差，然后去除UBM柱之间的种子结构的第二区域，从而在半导体管芯上形成UBM结构。