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81.发明公开公开(公告)号：US20240071521A1
公开(公告)日：2024-02-29
申请号：US18228291
申请日：2023-07-31
Applicant: Micron Technology, Inc.
Inventor： Dung Viet Nguyen , Patrick R. Khayat , Sivagnanam Parthasarathy , Zhengang Chen , Dheeraj Srinivasan
Abstract: Described are memory devices producing metadata characterizing the applied read voltage level with respect to voltage distributions. An example memory sub-system comprises: a memory device comprising a plurality of memory cells; and a controller coupled to the memory device, the controller to perform operations comprising: performing, using a read voltage level, a read strobe with respect to a subset of the plurality of memory cells; and receiving, from the memory device, one or more metadata values characterizing the read voltage level with respect to threshold voltage distributions of the subset of the plurality of memory cells, wherein the one or more metadata values reflect a conductive state of one or more bitlines connected to the subset of the plurality of memory cells.
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公开(公告)号：US11775381B2
公开(公告)日：2023-10-03
申请号：US17477859
申请日：2021-09-17
Applicant: Micron Technology, Inc.
Inventor： Zhengang Chen , Sivagnanam Parthasarathy
CPC classification number: G06F11/1004 , G06F3/0619 , G06F3/0659 , G06F3/0673
Abstract: A plurality of codewords are programmed to one or more memory pages of a memory sub-system. Each memory page of the memory sub-system is associated with a logical unit of a plurality of logical units of the memory sub-system and at least one of a plane of a plurality of planes of the memory sub-system or a block of a plurality of blocks of the memory sub-system. Each codeword of the plurality of codewords comprises host data and base parity bits. A plurality of additional parity bits are programmed to the one or more memory pages of the memory sub-system, wherein each additional parity bit of the plurality of additional parity bits is associated with a codeword of the plurality of standard codewords. A first set of redundancy metadata is generated corresponding to each of the additional parity bits. The first set of redundancy metadata is programmed to a memory page separate from any memory page storing the additional parity bits.
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公开(公告)号：US11709771B2
公开(公告)日：2023-07-25
申请号：US17739578
申请日：2022-05-09
Applicant: Micron Technology, Inc.
Inventor： Zhengang Chen , Jianmin Huang
CPC classification number: G06F12/0246 , G06F12/1408 , G06F13/1668 , G11C11/5628 , H04L9/0662 , H04L9/0869 , G06F2212/7207
Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, improved data distribution techniques decouple the scrambling key from a physical address to allow for copyback operations while maintaining data distribution requirements across a memory device. The controller may generate a seed value that is used by a scrambling algorithm to scramble the host-data and meta-data prior to the data being written. The seed value is then encoded and written to the page with encoded versions of the scrambled user data and meta-data—the random seed is written without scrambling the random seed.
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公开(公告)号：US20230052044A1
公开(公告)日：2023-02-16
申请号：US17584034
申请日：2022-01-25
Applicant: Micron Technology, Inc.
Inventor： Deping He , Zhengang Chen
Abstract: Methods, systems, and devices for a dynamic error control configuration for memory systems are described. The memory system may receive a read command and retrieve a set of data from a location of the memory system based on the read command. The memory system may perform a first type of error control operation on the set of data to determine whether the set of data includes one or more errors. If the set of data includes the one or more errors, the memory system may retrieve a second set of data from the location of the memory system and determine whether a syndrome weight satisfies a threshold. The memory system may perform a second type of error control operation on the second set of data based on determining that the syndrome weight satisfies the threshold.
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公开(公告)号：US20220376709A1
公开(公告)日：2022-11-24
申请号：US17880144
申请日：2022-08-03
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Wei Wu , Zhenlei Shen , Zhengang Chen
Abstract: Codewords of an error correcting code can be received. The codewords can be separated into multiple segments. The segments of the codewords can be distributed in an error correcting layout across a plurality of dies where at least a portion of the error correcting (EC) layout constitutes a first layout in the form of a Latin Square.
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Patent Agency Ranking
公开(公告)号：US20220326858A1
公开(公告)日：2022-10-13
申请号：US17228086
申请日：2021-04-12
Applicant: Micron Technology, Inc.
Inventor： Xiangang Luo , Zhengang Chen
IPC: G06F3/06
Abstract: A method that includes writing a plurality of codewords to a plurality of memory blocks of a memory device, where each of the plurality of codewords has a physical codeword index corresponding to a respective memory block in which each codeword is written, and assigning a virtual codeword index to each of the plurality of codewords to provide a plurality of virtual codeword indices, where assigning the virtual codeword index to each of the plurality of codewords is based, at least in part, on a location in a virtual block among a plurality of virtual blocks of memory cells corresponding to the physical codeword index of each codeword among the plurality of codewords.
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87.发明申请公开(公告)号：US20220294473A1
公开(公告)日：2022-09-15
申请号：US17831357
申请日：2022-06-02
Applicant: Micron Technology, Inc.
Inventor： Eyal En Gad , Zhengang Chen , Sivagnanam Parthasarathy , Yoav Weinberg
Abstract: A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after a threshold number of iterations is performed.
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公开(公告)号：US11327884B2
公开(公告)日：2022-05-10
申请号：US16837315
申请日：2020-04-01
Applicant: Micron Technology, Inc.
Inventor： Zhengang Chen , Jianmin Huang
Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, improved data distribution techniques decouple the scrambling key from a physical address to allow for copyback operations while maintaining data distribution requirements across a memory device. The controller may generate a seed value that is used by a scrambling algorithm to scramble the host-data and meta-data prior to the data being written. The seed value is then encoded and written to the page with encoded versions of the scrambled user data and meta-data—the random seed is written without scrambling the random seed.
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89.发明申请公开(公告)号：US20220006473A1
公开(公告)日：2022-01-06
申请号：US17447864
申请日：2021-09-16
Applicant: Micron Technology, Inc.
Inventor： Eyal En Gad , Zhengang Chen , Sivagnanam Parthasarathy , Yoav Weinberg
Abstract: A processing device in a memory system receives a request to read data from a memory device. In response to receiving the request, the processing device performs an iterative error correction process on the data, wherein at least one iteration after a first iteration in the error correction process uses a criterion that is based at least partially on a previous iteration or partial iteration, and wherein performing the iterative error correction process comprises flipping any bits in the data having an associated number of unsatisfied parity check equations that satisfies a threshold criterion associated with the previous iteration.
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公开(公告)号：US11204828B2
公开(公告)日：2021-12-21
申请号：US16215248
申请日：2018-12-10
Applicant: Micron Technology, Inc.
Inventor： Tingjun Xie , Zhengang Chen
Abstract: Described herein are embodiments related to one-direction error recovery flow (ERF) operations on memory components of memory systems. A processing device determines that data from a read operation is not successfully decoded because of a partial write of the data. The partial write results from a number of memory cells written as a first state and read as a second state. The processing device performs a one-direction ERF on the memory cells by monotonically adjusting a read voltage level for one or more re-read operations from a first discrete read voltage level towards a second read voltage level in a first direction until the data from the one or more re-read operations is successfully decoded. The first direction corresponds to an opposite direction of a state shift of the partial write. The processing device can also can determine a directional EBC and perform a refresh write if necessary.
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