公开(公告)号：US08120966B2

公开(公告)日：2012-02-21

申请号：US12658121

申请日：2010-02-03

申请人： Peter Wung Lee

发明人： Peter Wung Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/344 ,  G11C11/5635 ,  G11C16/0441

摘要： A method and apparatus for operating an array block of dual charge retaining transistor NOR flash memory cells by erasing the dual charge retaining transistor NOR flash memory cells to set their threshold voltage levels to prevent leakage current from corrupting data during a read operation. Erasure of the array block of NOR flash memory cells begins by selecting one of block section of the array block and erasing, erase verifying, over-erase verifying, and programming iteratively until the charge retaining transistors have their threshold voltages between the lower limit and the upper limit of the first program state. Other block sections are iteratively selected and erased, erased verified, over-erase verified, and programmed repeatedly until the charge retaining transistors have their threshold voltages between the lower limit and the upper limit of the first program state until the entire block has been erased and reprogrammed to a positive threshold level.

摘要翻译： 一种用于通过擦除双电荷保持晶体管NOR闪存单元来设置其阈值电压电平来操作双电荷保持晶体管NOR闪存单元的阵列块的方法和装置，以防止在读取操作期间漏电流损坏数据。 通过选择阵列块的块部分中的一个并擦除，擦除验证，过擦除验证和迭代地编程，直到电荷保持晶体管的阈值电压在下限和 第一程序状态的上限。 迭代地选择和擦除其他块部分，擦除确认，过擦除验证，并重复编程，直到电荷保持晶体管具有在第一编程状态的下限和上限之间的阈值电压，直到整个块被擦除为止， 重新编程为正阈值水平。

公开(公告)号：US20170352424A1

公开(公告)日：2017-12-07

申请号：US15615883

申请日：2017-06-07

申请人： Peter Wung Lee

发明人： Peter Wung Lee

IPC分类号： G11C16/10 ,  G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  G11C16/26

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3459 ,  G11C2211/5642

摘要： Provided are several preferred options of 3D hierarchical NAND arrays being formed in a (2D DL//3D LBL)⊥(3D CSL//3D WL) scheme and their associated 2D PBs are preferably formed right below the 3D array but on the reversed side of Psub so that the large silicon areas of most 2D peripheral circuits can be saved and the various 3D nLC NAND operations can be performed in more powerful pipeline and concurrent manner with a dramatic reduction in latency and power consumption.The preferred various 3D hierarchical NAND memories comprise a plurality of divided 3D sub-arrays for nLC storage, a plurality of 3D N-bit Cstring-based DCRs with minimum memory capacity to store 3×2n pages of program data when a 3-WL rotational nLC program scheme is adopted, and a plurality of distributed N-bit PBs with same number of LBL lines.Each hierarchical 3D array comprises a plurality of 3D LGs and each LG comprises a plurality of 3D blocks connected by N local 3D LBL metal lines and 3D CSL lines and each block further comprises N strings without a need of extra local precharge line of LGps lines as disclosed in prior granted patents.More number of distributed N-bit PBs would allow more powerful and flexible concurrent operations to be performed at the expense of taking larger silicon area in reversed side of Psub. By contrast, less number of distributed N-bit PBs would allow less powerful and flexible concurrent operations to be performed with a tradeoff of saving more silicon area in the reversed side of Psub. For performing any concurrent 3D NAND operation, a minimum two N-bit PB and 3×2n N-bit DCRs are required. Each N-bit SA comprises at least n+1 N-bit latches.Each bit of PB comprises one SA and one nLC-latch circuit. N-bit SA further comprises one N-bit Current-sensing circuit for performing ABL program, ABL page data loading in each N-bit CLBLs, ABL program-verify, ABL read on each 3D sub-array and ABL Write-back to each N-nit Cstring-based DCRs, and one N-bit Voltages-sensing circuit for performing HBL Recall from each page of selected Cstring-based N-bit DCR to N-bit PB. The operations of the 3D hierarchical NAND and Cstring-based DCR arrays and their associated distributed PBs can be performed in both concurrent and pipeline manners, regardless of a 2-poly floating-gate 3D cell or a 1-poly charge-trapping 3D cell, regardless of GIDL or FN-tunneling erase scheme, regardless of SLC, MLC, TLC and XLC storage types.

公开(公告)号：US09595319B2

公开(公告)日：2017-03-14

申请号：US15137284

申请日：2016-04-25

申请人： Peter Wung Lee

发明人： Peter Wung Lee

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  H01L27/115

CPC分类号： G11C11/5635 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24 ,  G11C16/3418 ,  G11C16/3445 ,  H01L27/11556 ,  H01L27/11582

摘要： A novel 2D/3D hierarchical-BL NAND array with at least one plane on independent Psubstrate comprising a plurality of LG groups respectively associated with a plurality of local bit lines (LBLs) laid at a level below a plurality of broken or non-broken global bit lines (GBLs) connected to Page Buffer. Each LG group includes multiple blocks and connects an independent power supply line to each of the plurality of LBLs. Each block including N-bit 2D/3D NAND strings each with S cells connected in series and terminated by two string-select devices and coupled to a common source line. In particular, random-size partial-block WLs are selected from each block of randomly selected LG groups of one plane of the 2D/3D NAND array for erase at the same time with border WLs being optionally preread and program into another plane of the 2D/3D NAND array or optionally saved off-chip and wrote back for data security.

摘要翻译： 一种新颖的2D / 3D分层BL NAND阵列，其独立的基板上具有至少一个平面，包括分别与多个局部位线（LBL）相关联的多个LG组，所述多个局部位线布置在低于多个破碎或非断开全局 连接到页面缓冲区的位线（GBL）。 每个LG组包括多个块，并且将独立电源线连接到多个LBL中的每一个。 每个块包括N位2D / 3D NAND串，每个NAND串都具有串联连接的S个单元，并由两个串选择器件终止并耦合到公共源极线。 特别地，随机大小的部分块WL从2D / 3D NAND阵列的一个平面的随机选择的LG组的每个块中选择同时进行擦除，边界WL可选地被预读，并且编程到2D的另一个平面 / 3D NAND阵列或可选地保存在片外，并回写数据安全。

公开(公告)号：US09524773B2

公开(公告)日：2016-12-20

申请号：US14966894

申请日：2015-12-11

申请人： Peter Wung Lee

发明人： Peter Wung Lee

IPC分类号： G11C11/56 ,  G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C7/10 ,  H01L27/115

CPC分类号： G11C11/5635 ,  G11C7/1039 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/1157 ,  H01L27/11582

摘要： This invention provides a 2-level BL-hierarchical NAND memory architecture and associated concurrent operations applicable to both 2D and 3D HiNAND2 memory arrays. New Latch designs in Block-decoder and Segment-decoder with one common dedicated metal0 power line per one 2N-bit dynamic page buffer (DPB) formed in corresponding 2N broken-LBL metal1 line capacitors for Program and per one 2N-bit Segment DPB formed in corresponding 2N local LBL metal1 line capacitors for Read are provided for performing concurrent and pipeline operations of multiple-WL Program, Read, Erase-Verify, and Program-Verify in dispersed Blocks in a same or multiple different NAND planes with much enhanced array flexibility and multiple-fold performance improvements.

公开(公告)号：US09183940B2

公开(公告)日：2015-11-10

申请号：US14283209

申请日：2014-05-20

申请人： Peter Wung Lee

发明人： Peter Wung Lee

IPC分类号： G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C16/34 ,  G11C11/56

CPC分类号： G11C16/26 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C2211/5641

摘要： A HiNAND array with a hierarchical-BL scheme configured to divide a large global bit line (GBL) capacitance into J number of small local bit line (LBL) capacitances for reducing bit line precharge voltage and discharge time to achieve faster Read and Program-Verify speed, lower power consumption, lower latency, and lower word line disturbance for a reliable DRAM-like latch sensing. A reduced precharge voltage can be increased by M-fold (M≧2) using a Multiplier between each bitline and each Latch sense amplifier (SA). Between each Multiplier and each Latch SA, there is a Connector with two optional designs for either fully passing a sense voltage to the Latch SA with a same-polarity and value or reversing the polarity the sensing voltage with additional amplification. The Latch SA is configured to transfer stored threshold states of a memory cell into a bit of a page buffer.

摘要翻译： 具有分层BL方案的HiNAND阵列被配置为将大的全局位线（GBL）电容分成J个小的局部位线（LBL）电容，以减少位线预充电电压和放电时间，以实现更快的读取和编程验证 速度，更低的功耗，更低的延迟和更低的字线干扰，以实现可靠的类DRAM锁存检测。 使用每个位线和每个锁存读出放大器（SA）之间的乘数，可以减小预充电电压M倍（M≥2）。 在每个乘法器和每个锁存器SA之间，具有两个可选设计的连接器，用于将具有相同极性和值的Latch SA的感测电压完全传递，或者通过附加放大来反转感测电压的极性。 Latch SA被配置为将存储器单元的存储的阈值状态传送到页缓冲器的位中。

公开(公告)号：US09177658B2

公开(公告)日：2015-11-03

申请号：US14546294

申请日：2014-11-18

申请人： Peter Wung Lee ,  Hsing-Ya Tsao

发明人： Peter Wung Lee ,  Hsing-Ya Tsao

IPC分类号： G11C11/04 ,  G11C16/14 ,  G11C16/34 ,  G11C16/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26

CPC分类号： G11C16/14 ,  G11C16/0425 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C2216/14

摘要： An one-transistor-one-bit (1T1b) Flash-based EEPROM cell is provided along with improved key operation schemes including applying a negative word line voltage and a reduced bit line voltage for perform erase operation, which drastically reduces the high voltage stress on each cell for enhancing the Program/Erase cycles while reducing cell size. An array made by the 1T1b Flash-based EEPROM cells can be operated with Half-page or Full-page divided programming and pre-charging period for each program cycle. Utilizing PGM buffer made of Vdd devices in the cell array further save silicon area. Additionally, a two-transistor-two-bit (2T2b) EEPROM cell derived from the 1T1b cell is disclosed with additional cell size reduction but with the operation of program and erase the same as that for the 1T1b cells with benefits of no process change but much enhanced storage density, superior Program/Erase endurance cycle, and capability for operating in high temperature environment.

摘要翻译： 提供了一个单晶体管一位（1T1b）基于闪存的EEPROM单元，以及改进的键操作方案，包括施加负字线电压和降低的位线电压用于执行擦除操作，这大大降低了高压应力 每个单元用于增强编程/擦除周期，同时减小单元大小。 由1T1b闪存的EEPROM单元制成的阵列可以在每个程序周期的半页或全页分割编程和预充电周期下进行操作。 在单元阵列中利用由Vdd器件制成的PGM缓冲器进一步节省了硅面积。 另外，公开了从1T1b单元得到的双晶体二极管2位（2T2b）EEPROM单元，其额外的单元尺寸减小，但是与1T1b单元相同的编程和擦除操作的优点在于没有处理变化， 大大增强了存储密度，卓越的程序/擦除耐久循环，以及在高温环境下运行的能力。

公开(公告)号：US20140085978A1

公开(公告)日：2014-03-27

申请号：US14037356

申请日：2013-09-25

申请人： Peter Wung Lee

发明人： Peter Wung Lee

IPC分类号： G11C14/00

CPC分类号： G11C14/0063 ,  G11C11/005 ,  G11C15/046 ,  G11C16/0483 ,  H01L21/0262 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/115

摘要： Several preferred embodiments of 1S1F 16T NVSRAM, 1S1F 20T NVSRAM, 1S2F 22T NVSRAM, 1S2F 14T NVSRAM cells are proposed, regardless of 1-poly, 2-poly, PMOS or NOS flash cell structures. Two separate sourcelines for the paired flash Strings are also proposed for easy adding ability for the NVSRAM circuit to detect the marginally erased Vt0 and marginally programmed Vt1 of the paired flash cell. By increasing an resistance added to common SRAM power line, the pull-down current through flash Strings to grounding source line can be made much larger than the pull-up current to improve SFwrite program operation. Simple method by increasing flash cell channel length to effectively enhance coupling area is applied to secure SRAM-to-Flash store operation under self-boost-program-inhibit scheme. 1S2F architecture also provide flexibility for alternate erasing and programming during both a recall and store operation.

摘要翻译： 提出了1S1F 16T NVSRAM，1S1F 20T NVSRAM，1S2F 22T NVSRAM，1S2F 14T NVSRAM单元的几个优选实施例，而不管1-聚，2-聚，PMOS或NOS闪存单元结构如何。 还提出了用于配对闪存串的两个独立的源线，用于容易地添加NVSRAM电路检测成对闪存单元的边缘擦除Vt0和边缘编程Vt1的能力。 通过增加普通SRAM电源线的电阻，通过闪光串的下拉电流到接地源线可以比上拉电流大得多，以改善SFwrite程序运行。 通过增加闪存单元通道长度以有效增强耦合面积的简单方法被应用于在自增强编程抑制方案下保护SRAM到闪存存储器操作。 1S2F架构还为召回和存储操作期间的交替擦除和编程提供了灵活性。

公开(公告)号：US08582363B2

公开(公告)日：2013-11-12

申请号：US12931395

申请日：2011-01-31

申请人： Peter Wung Lee

发明人： Peter Wung Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/3409 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0458 ,  G11C16/08 ,  G11C16/24 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5621

摘要： A method and apparatus for operating an array block of dual charge retaining transistor NOR flash memory cells by erasing the dual charge retaining transistor NOR flash memory cells to set their threshold voltage levels to prevent leakage current from corrupting data during a read operation. Erasure of the array block of NOR flash memory cells begins by selecting one of block section of the array block and strongly and deeply erasing, over-erase verifying, and programming iteratively until the charge retaining transistors have their threshold voltages between the lower voltage limit and the upper voltage limit of the first program state. Other block sections are iteratively selected and erased, over-erase verified, and programmed repeatedly until the charge retaining transistors have their threshold voltages between the lower voltage limit and the upper voltage limit of the first program state until the entire block has been erased and reprogrammed to a positive threshold level.

摘要翻译： 一种用于通过擦除双电荷保持晶体管NOR闪存单元来设置其阈值电压电平来操作双电荷保持晶体管NOR闪存单元的阵列块的方法和装置，以防止在读取操作期间漏电流损坏数据。 NOR闪存单元的阵列块的擦除通过选择阵列块的块部分中的一个并且强烈且深入擦除，过擦除验证和迭代地编程，直到电荷保持晶体管的阈值电压在较低的电压极限和 第一程序状态的上限电压。 迭代地选择和擦除其他块部分，过度擦除验证，并重复编程，直到电荷保持晶体管的阈值电压在第一编程状态的较低电压限制和上限电压之间，直到整个块被擦除并重新编程 达到正阈值水平。

公开(公告)号：US20120195123A1

公开(公告)日：2012-08-02

申请号：US12931395

申请日：2011-01-31

申请人： Peter Wung Lee

发明人： Peter Wung Lee

IPC分类号： G11C16/16 ,  G11C16/12 ,  G11C16/14 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C16/3409 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0458 ,  G11C16/08 ,  G11C16/24 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5621

摘要： A method and apparatus for operating an array block of dual charge retaining transistor NOR flash memory cells by erasing the dual charge retaining transistor NOR flash memory cells to set their threshold voltage levels to prevent leakage current from corrupting data during a read operation. Erasure of the array block of NOR flash memory cells begins by selecting one of block section of the array block and strongly and deeply erasing, over-erase verifying, and programming iteratively until the charge retaining transistors have their threshold voltages between the lower voltage limit and the upper voltage limit of the first program state. Other block sections are iteratively selected and erased, over-erase verified, and programmed repeatedly until the charge retaining transistors have their threshold voltages between the lower voltage limit and the upper voltage limit of the first program state until the entire block has been erased and reprogrammed to a positive threshold level.

摘要翻译： 一种用于通过擦除双电荷保持晶体管NOR闪存单元来设置其阈值电压电平来操作双电荷保持晶体管NOR闪存单元的阵列块的方法和装置，以防止在读取操作期间漏电流损坏数据。 NOR闪存单元的阵列块的擦除通过选择阵列块的块部分中的一个并且强烈且深入擦除，过擦除验证和迭代地编程，直到电荷保持晶体管的阈值电压在较低的电压极限和 第一程序状态的上限电压。 迭代地选择和擦除其他块部分，过度擦除验证，并重复编程，直到电荷保持晶体管的阈值电压在第一编程状态的较低电压限制和上限电压之间，直到整个块被擦除并重新编程 达到正阈值水平。

公开(公告)号：US09659636B2

公开(公告)日：2017-05-23

申请号：US14806629

申请日：2015-07-22

申请人： Peter Wung Lee

发明人： Peter Wung Lee

IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  G11C7/14 ,  G11C7/18 ,  G11C29/50

CPC分类号： G11C11/5635 ,  G11C7/14 ,  G11C7/18 ,  G11C11/56 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/50 ,  G11C2029/5002

摘要： A YUKAI NAND array comprising multiple strings associated with hierarchical global/local bit lines (GBL/LBL) and each string being associated with one LBL and having adjacent LBL as a dedicated local source line (LSL) without a common source line to connect all strings. Each of the LBLs is interleavingly associated with either an Odd or Even string selected via one pair of dummy cells inserted in each string and is used as one on-chip PCACHE register with full BL-shielding without wasting extra silicon area to allow batch-based multiple concurrent MLC All-BL, All-Vtn-Program and Alternative-WL program, Odd/Even read and verify operations with options of providing individual and common VSL-based Vt-compensation and VLBL compensations to mitigate high WL-WL and BL-BL coupling effects. Bias conditions in each string are provided to correctly sense highly-negative erase-verify voltage, multiple negative program-verify voltages and without VDS punch-through, breakdown and body-effect in both boundary and non-boundary WLs cells.