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    ASYMMETRIC WRITE SCHEME FOR MAGNETIC BIT CELL ELEMENTS
    81.
    发明申请
    ASYMMETRIC WRITE SCHEME FOR MAGNETIC BIT CELL ELEMENTS 有权
    磁性元件元件的不对称写入方案

    公开(公告)号：US20140063933A1

    公开(公告)日：2014-03-06

    申请号：US14076427

    申请日：2013-11-11

    Applicant: QUALCOMM Incorporated

    Inventor： Xiaochun Zhu ,  Hari M. Rao ,  Jung Pill Kim ,  Seung Hyuk Kang

    IPC: G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1693

    Abstract: A first write driver applies a first voltage above a fixed potential to a first terminal. A second write driver applies a second voltage that is higher above the fixed potential than the first voltage to a second terminal. There is at least one magnetic tunnel junction (MTJ) structure coupled at the first terminal at a first side to the first write driver and coupled at the second terminal at a second side to the second write driver. The first side of the MTJ structure receives the first voltage and the second side of the MTJ structure receives a ground voltage to change from a first state to a second state. The second side of the MTJ structure receives the second voltage and the first side of the MTJ structure receives the ground voltage to change from the second state to the first state.

    Abstract translation: 第一写入驱动器将高于固定电位的第一电压施加到第一端子。 第二写入驱动器将比固定电位高于第一电压的第二电压施加到第二端子。 至少有一个磁隧道结（MTJ）结构在第一端处的第一端耦合到第一写入驱动器，并且在第二端处的第二端耦合到第二写入驱动器。 MTJ结构的第一侧接收第一电压，并且MTJ结构的第二侧接收地电压以从第一状态变为第二状态。 MTJ结构的第二面接收第二电压，并且MTJ结构的第一侧接收地电压以从第二状态变为第一状态。

    CONFIGURABLE MEMORY ARRAY
    82.
    发明申请
    CONFIGURABLE MEMORY ARRAY 审中-公开
    可配置内存阵列

    公开(公告)号：US20140043924A1

    公开(公告)日：2014-02-13

    申请号：US14056990

    申请日：2013-10-18

    Applicant: QUALCOMM Incorporated

    Inventor： Jung Pill Kim ,  Hari M. Rao ,  Xiaochun Zhu ,  Xia Li ,  Seung Hyuk Kang

    IPC: G11C11/16 ,  H01L43/12

    CPC classification number: G11C11/1677 ,  G11C8/08 ,  G11C8/14 ,  G11C11/16 ,  G11C11/161 ,  G11C29/18 ,  G11C29/30 ,  G11C2029/1202 ,  G11C2029/2602 ,  H01L43/12

    Abstract: Embodiments disclosed include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of storage elements have a first subset of storage elements electrically decoupled from the memory array and a second subset of storage elements coupled to the memory array. The memory array further includes a plurality of bit cells, each including one storage element from the second subset of storage elements coupled to at least two transistors. The bit cells are coupled to the plurality of bit lines and the plurality source lines. Each transistor is coupled to one word line. The memory array can further include logic to select a high performance mode and a high density mode.

    Abstract translation: 所公开的实施例包括具有多个位线和多个排列成列的源极线的存储器阵列。 多行字线被排列成行。 多个存储元件具有与存储器阵列电分离的存储元件的第一子集和耦合到存储器阵列的存储元件的第二子集。 存储器阵列还包括多个位单元，每个位单元包括来自耦合到至少两个晶体管的存储元件的第二子集的一个存储元件。 位单元耦合到多个位线和多个源极线。 每个晶体管耦合到一个字线。 存储器阵列还可以包括选择高性能模式和高密度模式的逻辑。

    ROW-DECODER CIRCUIT AND METHOD WITH DUAL POWER SYSTEMS
    83.
    发明申请
    ROW-DECODER CIRCUIT AND METHOD WITH DUAL POWER SYSTEMS 审中-公开
    ROW-DECODER电路和双电源系统的方法

    公开(公告)号：US20130314980A1

    公开(公告)日：2013-11-28

    申请号：US13953780

    申请日：2013-07-30

    Applicant: QUALCOMM Incorporated

    Inventor： Jung Pill Kim ,  Taehyun Kim ,  Seung H. Kang

    IPC: G11C11/16

    CPC classification number: G11C11/1653 ,  G11C8/08 ,  G11C8/10 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

    Abstract: A Spin-Transfer-Torque Magnetic Random Access Memory includes a dual-voltage row decoder with charge sharing for read operations. The dual-voltage row decoder with charge sharing for read operations reduces read-disturbance failure rates and provides a robust macro design with improved yields. Voltage from one of the power supplies can be applied during a write operation.

    Abstract translation: 旋转转矩磁性随机存取存储器包括具有用于读取操作的电荷共享的双电压行解码器。 具有用于读取操作的电荷共享的双电压行解码器可降低读取干扰故障率，并提供强大的宏设计，提高产量。 在写入操作期间可以应用来自其中一个电源的电压。

    MAGNETIC RANDOM ACCESS MEMORY (MRAM)LAYOUT WITH UNIFORM PATTERN
    84.
    发明申请
    MAGNETIC RANDOM ACCESS MEMORY (MRAM)LAYOUT WITH UNIFORM PATTERN 有权
    具有均匀图案的磁性随机存取存储器（MRAM）布局

    公开(公告)号：US20130235639A1

    公开(公告)日：2013-09-12

    申请号：US13869086

    申请日：2013-04-24

    Applicant: QUALCOMM INCORPORATED

    Inventor： Kangho Lee ,  Taehyun Kim ,  Xia Li ,  Jung Pill Kim ,  Seung H. Kang

    IPC: G11C5/02 ,  G11C5/08

    CPC classification number: G11C5/025 ,  G11C5/08 ,  G11C11/165 ,  H01L27/0207 ,  Y10T29/49117

    Abstract: A large scale memory array includes a. uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects.

    Abstract translation: 大型存储器阵列包括a。 均匀大小的虚拟位单元和有源位单元的统一模式。 大规模存储器阵列中的子阵列由虚拟位单元分隔开。 信号分配电路形成为具有对应于虚拟位单元的宽度或高度的宽度或高度，使得信号分配电路占据与虚拟位单元相同的覆盖区，而不会破坏整个大规模阵列上的均匀图案。 类似大小或大于标准尺寸位单元的边缘虚拟单元可以放置在大规模阵列的边缘周围，以进一步减少图案负载影响。

    Offset-cancellation sensing circuit (OCSC)-based non-volatile (NV) memory circuits
    85.
    发明授权
    Offset-cancellation sensing circuit (OCSC)-based non-volatile (NV) memory circuits 有权

    公开(公告)号：US10319425B1

    公开(公告)日：2019-06-11

    申请号：US15939514

    申请日：2018-03-29

    Applicant: QUALCOMM Incorporated ,  Yonsei University, University-Industry Foundation

    Inventor： Seong-Ook Jung ,  Byungkyu Song ,  Sungryul Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

    IPC: G11C11/16

    Abstract: Offset-cancellation sensing circuit (OCSC)-based Non-volatile (NV) memory circuits are disclosed. An OCSC-based NV memory circuit includes a latch circuit configured to latch a memory state from an input signal. The OCSC-based NV memory circuit also includes a sensing circuit that includes NV memory devices configured to store the latched memory state in the latch circuit for restoring the memory state in the latch circuit when recovering from a reduced power level in an idle mode. To avoid the need to increase transistor size in the sensing circuit to mitigate restoration degradation, the sensing circuit is also configured to cancel an offset voltage of a differential amplifier in the sensing circuit. In other exemplary aspects, the NV memory devices are included in the sensing circuit and coupled to the differential transistors as NMOS transistors in the differential amplifier, eliminating contribution of offset voltage from other differential PMOS transistors not included.

    MAGNETORESISTIVE (MR) SENSORS EMPLOYING DUAL MR DEVICES FOR DIFFERENTIAL MR SENSING
    86.
    发明申请
    MAGNETORESISTIVE (MR) SENSORS EMPLOYING DUAL MR DEVICES FOR DIFFERENTIAL MR SENSING 审中-公开

    公开(公告)号：US20180372685A1

    公开(公告)日：2018-12-27

    申请号：US16057452

    申请日：2018-08-07

    Applicant: QUALCOMM Incorporated

    Inventor： Wei-Chuan Chen ,  Jung Pill Kim ,  Seung Hyuk Kang

    IPC: G01N27/74 ,  G01R33/09 ,  B82Y25/00

    Abstract: Magnetoresistive (MR) sensors employing dual MR devices for differential MR sensing are provided. These MR sensors may be used as biosensors to detect the presence of biological materials as an example. An MR sensor includes dual MR sensor devices that may be tunnel magnetoresistive (TMR) devices or giant magnetoresistive (GMR) devices as examples. The MR devices are arranged such that a channel is formed between the MR devices for receiving magnetic nanoparticles. A magnetic stray field generated by the magnetic nanoparticles causes free layers in the MR devices to rotate in opposite directions, thus causing differential resistances between the MR devices for greater sensing sensitivity. Further, as another aspect, by providing the channel between the MR devices, the magnetic stray field generated by the magnetic nanoparticles can more easily rotate the magnetic moment orientation of the free layers in the MR devices, thus further increasing sensitivity.

    Physically unclonable function based on comparison of MTJ resistances
    88.
    发明授权
    Physically unclonable function based on comparison of MTJ resistances 有权

    公开(公告)号：US09870811B2

    公开(公告)日：2018-01-16

    申请号：US15185441

    申请日：2016-06-17

    Applicant: QUALCOMM Incorporated

    Inventor： Peiyuan Wang ,  Jung Pill Kim ,  Jimmy Jianan Kan ,  Chando Park ,  Seung Kang

    IPC: G11C11/16 ,  G11C17/02

    CPC classification number: G11C11/1675 ,  G11C7/20 ,  G11C11/1693 ,  G11C11/1695 ,  G11C14/0081

    Abstract: In a particular aspect, an apparatus includes a magnetic random access memory (MRAM) cell including a pair of cross coupled inverters including a first inverter and a second inverter. The first inverter includes a first transistor coupled to a first node and a second transistor coupled to the first node. The second inverter includes a third transistor coupled to a second node and a fourth transistor coupled to the second node. The MRAM cell includes a first magnetic tunnel junction (MTJ) element coupled to the second transistor and a second MTJ element coupled to the fourth transistor. The apparatus further includes a voltage initialization circuit coupled to the MRAM cell. The voltage initialization circuit is configured to substantially equalize voltages of the first node and the second node in response to an initialization signal.

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