公开(公告)号：US20100330763A1

公开(公告)日：2010-12-30

申请号：US12493549

申请日：2009-06-29

申请人： Gregory G. Freeman ,  Shreesh Narasimha ,  Ning Su ,  Hasan M. Nayfeh ,  Nivo Rovedo ,  Werner A. Rausch ,  Jian Yu

发明人： Gregory G. Freeman ,  Shreesh Narasimha ,  Ning Su ,  Hasan M. Nayfeh ,  Nivo Rovedo ,  Werner A. Rausch ,  Jian Yu

IPC分类号： H01L21/336

CPC分类号： H01L21/823425 ,  H01L21/26586 ,  H01L21/823412 ,  H01L29/66492 ,  H01L29/66659

摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, respectively, a first and a second gate conductor of a first and a second transistor and have, respectively, a top surface, a first side, and a second side with the second side being opposite to the first side; performing a first halo implantation from the first side of the first and second gate-mask stacks at a first angle while applying the first gate-mask stack in preventing the first halo implantation from reaching a first source/drain region of the second transistor, wherein the first angle is equal to or larger than a predetermined value; and performing a second halo implantation from the second side of the first and second gate-mask stacks at a second angle, thereby creating halo implant in a second source/drain region of the second transistor, wherein the first and second angles are measured against a normal to the substrate.

摘要翻译： 本发明提供了形成非对称场效应晶体管的方法。 该方法包括在半导体衬底的顶部上形成至少第一和第二栅极掩模叠层，其中第一和第二栅极掩模叠层至少分别包括第一和第二栅极掩模叠层的第一和第二栅极导体 分别具有顶表面，第一侧和第二侧，第二侧与第一侧相对; 以第一角度从第一和第二栅极掩模叠层的第一侧进行第一光晕注入，同时施加第一栅极掩模叠层以防止第一光晕注入到达第二晶体管的第一源极/漏极区域，其中 第一角度等于或大于预定值; 以及以第二角度从所述第一和第二栅极掩模叠层的第二侧执行第二光晕注入，从而在所述第二晶体管的第二源极/漏极区域中产生晕轮注入，其中所述第一和第二角度是针对 与基底垂直。

公开(公告)号：US07732270B2

公开(公告)日：2010-06-08

申请号：US11972964

申请日：2008-01-11

申请人： Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Haining Yang ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Haining Yang ,  Huilong Zhu

IPC分类号： H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L29/66772 ,  Y10S438/938

摘要： The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.

摘要翻译： 本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET提供增加的横向应力状态以及用于制造这种器件的方法。 本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到器件上并施加与第一氮化硅衬垫相邻的第二氮化硅衬垫，其中至少一个 第一和第二氮化硅衬垫在第一和第二氮化硅衬里中的至少一个之下的硅沟道中引起横向应力。

公开(公告)号：US07709910B2

公开(公告)日：2010-05-04

申请号：US11738666

申请日：2007-04-23

申请人： William K. Henson ,  Paul Chung-Muh Chang ,  Dureseti Chidambarrao ,  Ricardo A. Donaton ,  Yaocheng Liu ,  Shreesh Narasimha ,  Amanda L. Tessier

发明人： William K. Henson ,  Paul Chung-Muh Chang ,  Dureseti Chidambarrao ,  Ricardo A. Donaton ,  Yaocheng Liu ,  Shreesh Narasimha ,  Amanda L. Tessier

IPC分类号： H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/28097 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7843

摘要： A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride liner contacts only the outer sidewalls of the gate spacer, while not contacting inner sidewalls, or only a small area of the inner sidewalls of the gate spacer, therefore applying substantially the same level of stress to the channel of the MOSFET as conventional MOSFETs. The volume surrounded by the gate spacer and located above the gate electrode is either filled with a low-k dielectric material or occupied by a cavity having a dielectric constant of substantially 1.0. The reduced height of the gate electrode and the low-k dielectric gate filler or the cavity reduces the parasitic capacitance.

摘要翻译： 半导体结构在栅电极和接触通孔之间提供较低的寄生电容，同时通过降低栅极电极的高度并保持与栅极间隔件基本上相同的高度，提供与常规MOSFET相同的氮化物衬垫施加的基本相同的应力水平。 氮化物衬垫仅接触栅极间隔物的外侧壁，而不接触内侧壁，或者仅接触栅极隔离物的内侧壁的小面积，因此与常规MOSFET相比施加与MOSFET的通道基本相同的应力水平 。 由栅极间隔物围绕并位于栅极电极上方的体积填充有低k电介质材料或由具有基本上1.0的介电常数的空腔占据。 栅电极和低k电介质栅极填充物或空腔的降低的高度减小了寄生电容。

公开(公告)号：US20090178012A1

公开(公告)日：2009-07-09

申请号：US11971015

申请日：2008-01-08

申请人： Dureseti Chidambarrao ,  Gerald M. Davidson ,  Paul A. Hyde ,  Judith H. McCullen ,  Shreesh Narasimha

发明人： Dureseti Chidambarrao ,  Gerald M. Davidson ,  Paul A. Hyde ,  Judith H. McCullen ,  Shreesh Narasimha

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A system and method for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device in a circuit to be modeled, the transistor including an active device (RX) area over which the gate is formed and over which the conductive line feature extends. The method includes providing an analytical model representation including a function for modeling a lithographic flare effect impacting the active device area width; and, from the modeling function, relating an effective change in active device area width (deltaW adder) as a function of a distance from a defined edge of the RX area. Then, transistor model parameter values in a transistor compact model for the device are updated to include deltaW adder values to be added to a built-in deltaW value. A netlist used in a simulation includes the deltaW adder values to more accurately describe the characteristics of the transistor device being modeled including modeling of lithographic corner rounding effect on transistor device parametrics.

摘要翻译： 一种用于建模半导体晶体管器件结构的系统和方法，所述半导体晶体管器件结构具有设计长度的导线特征，所述导线特征与待建模的电路中的晶体管器件的栅极连接，所述晶体管包括有源器件（RX） 形成并且其上延伸有导线特征。 该方法包括提供分析模型表示，其包括用于建模影响有源器件区域宽度的光刻火炬效应的功能; 并且从建模功能将有源器件区域宽度（deltaW加法器）的有效变化与距离RX区域的限定边缘的距离的函数相关联。 然后，器件的晶体管紧凑型模型中的晶体管模型参数值被更新为包括要添加到内置deltaW值的ΔW加法器值。 在模拟中使用的网表包括deltaW加法器值，以更精确地描述被建模的晶体管器件的特性，包括对晶体管器件参数的光刻拐角舍入效应的建模。

公开(公告)号：US20070106968A1

公开(公告)日：2007-05-10

申请号：US11164044

申请日：2005-11-08

申请人： James Culp ,  Lars Liebmann ,  Rajeev Malik ,  K. Paul Muller ,  Shreesh Narasimha ,  Stephen Runyon ,  Patrick Williams

发明人： James Culp ,  Lars Liebmann ,  Rajeev Malik ,  K. Paul Muller ,  Shreesh Narasimha ,  Stephen Runyon ,  Patrick Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： An iterative timing analysis is analytically performed before a chip is fabricated, based on a methodology using optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time sensitive devices. The additional mask is used as a selective trim to form shortened gate lengths or wider metal lines for the selected, predetermined transistors, affecting the threshold voltages and the RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. The analysis methodology is repeated as often as needed to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants until manufacturing limits are reached. A mask is made for the selected critical devices using OPC techniques.

摘要翻译： 基于使用光学邻近校正技术的方法，在制造芯片之前分析地执行迭代时序分析，以缩短栅极长度并调整关键时间敏感器件的金属线宽度和接近距离。 附加掩模用作选择性修整以形成用于所选择的预定晶体管的缩短的栅极长度或更宽的金属线，影响所选器件的阈值电压和RC时间常数。 标记形状识别构成关键定时路径中的装置的电路的预定子组。 根据需要经常重复分析方法，以在缩短设计的栅极长度和修改的RC定时常数的情况下改善电路的时序，直到达到制造限值。 使用OPC技术为所选的关键设备制作掩码。

公开(公告)号：US07189644B2

公开(公告)日：2007-03-13

申请号：US10763308

申请日：2004-01-23

申请人： Shreesh Narasimha ,  Patricia A. O'Neil

发明人： Shreesh Narasimha ,  Patricia A. O'Neil

IPC分类号： H01L21/4763 ,  H01L29/76

CPC分类号： H01L29/66507 ,  H01L29/665 ,  H01L29/6656

摘要： The present invention relates to a Complementary Metal Oxide Semiconductor (CMOS) device having a lower external resistance and a method for manufacturing the CMOS device. The inventive MOSFET is produced by forming first suicide regions in a substrate as well as atop surface of a gate region and forming second silicide regions where second silicide thickness is greater than the first silicide thickness. The inventive method produces a low resistance first silicide in close proximity to the channel region of the device, where the incorporation of the first silicide decreases the external resistance of the device while the incorporation of the second silicide produces low sheet resistance interconnects.

摘要翻译： 本发明涉及具有较低外部电阻的互补金属氧化物半导体（CMOS）器件及其制造方法。 本发明的MOSFET通过在衬底以及栅极区域的顶表面上形成第一硅化物区域并形成其中第二硅化物厚度大于第一硅化物厚度的第二硅化物区域来制造。 本发明的方法在器件的沟道区域附近产生低电阻的第一硅化物，其中掺入第一硅化物降低了器件的外部电阻，同时掺入第二硅化物产生低的薄层电阻互连。

公开(公告)号：US20060231899A1

公开(公告)日：2006-10-19

申请号：US11108012

申请日：2005-04-15

申请人： Leland Chang ,  Shreesh Narasimha ,  Norman Rohrer ,  Jeffrey Sleight

发明人： Leland Chang ,  Shreesh Narasimha ,  Norman Rohrer ,  Jeffrey Sleight

IPC分类号： H01L29/94

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L27/1207

摘要： The present invention provides a 6T-SRAM semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.

摘要翻译： 本发明提供了一种6T-SRAM半导体结构，其包括具有SOI区域和体积-Si区域的衬底，其中SOI区域和体积-Si区域具有相同或不同的晶体取向; 将SOI区域与体Si区域分离的隔离区域; 以及位于SOI区域中的至少一个第一器件和位于本体Si区域中的至少一个第二器件。 SOI区域在绝缘层顶部具有硅层。 体硅区域还包括位于第二器件下面的阱区域和与阱区域的接触，其中接触稳定浮体效应。 阱接触还用于控制体Si区域中的FET的阈值电压，以优化由SOI和体Si区域FET的组合构建的SRAM单元的功率和性能。

公开(公告)号：US07071072B2

公开(公告)日：2006-07-04

申请号：US10710001

申请日：2004-06-11

申请人： Renee T. Mo ,  Shreesh Narasimha

发明人： Renee T. Mo ,  Shreesh Narasimha

IPC分类号： H01L21/76

CPC分类号： H01L21/76283

摘要： Shallow trench isolation structures are formed without CMP by depositing a thick pad nitride and depositing oxide trench fill material such that: a) the material in the trenches is above the silicon surface by a process margin that allows for removal of trench fill in subsequent front end steps so that the final trench fill level is substantially coplanar with the silicon; and b) the oxide on the interior walls is easily removed, so that the pad nitride is removed in a wet etch.

摘要翻译： 通过沉积厚衬垫氮化物和沉积氧化物沟槽填充材料形成浅沟槽隔离结构，使得：a）沟槽中的材料在硅表面之上，具有允许在随后的前端去除沟槽填充的工艺余量 使得最终沟槽填充水平基本上与硅共面; 和b）内壁上的氧化物容易去除，使得衬垫氮化物在湿蚀刻中被去除。

公开(公告)号：US20060128091A1

公开(公告)日：2006-06-15

申请号：US10905025

申请日：2004-12-10

申请人： Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Haining Yang ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Haining Yang ,  Huilong Zhu

IPC分类号： H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L29/66772 ,  Y10S438/938

摘要： The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.

摘要翻译： 本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET提供增加的横向应力状态以及用于制造这种器件的方法。 本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到器件上并施加与第一氮化硅衬垫相邻的第二氮化硅衬垫，其中至少一个 第一和第二氮化硅衬垫在第一和第二氮化硅衬里中的至少一个之下的硅沟道中引起横向应力。

公开(公告)号：US20060057797A1

公开(公告)日：2006-03-16

申请号：US11266855

申请日：2005-11-04

申请人： Atul Ajmera ,  Andres Bryant ,  Percy Gilbert ,  Michael Gribelyuk ,  Edward Maciejewski ,  Renee Mo ,  Shreesh Narasimha

发明人： Atul Ajmera ,  Andres Bryant ,  Percy Gilbert ,  Michael Gribelyuk ,  Edward Maciejewski ,  Renee Mo ,  Shreesh Narasimha

IPC分类号： H01L21/8238

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains. The plug seals and encapsulates the dielectric layer underlying each said spacer, thus preventing the dielectric material from being undercut during the subsequent pre-silicide clean process. By preventing undercut, this invention also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide. Thus, the integration of thin-spacer transistor geometries, which are required for improving transistor drive current, is enabled.