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    Dual row-column major dram
    84.
    发明授权
    Dual row-column major dram 有权

    公开(公告)号：US11568920B2

    公开(公告)日：2023-01-31

    申请号：US15713587

    申请日：2017-09-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng

    IPC: G06F3/00 ,  G11C11/408 ,  G06F3/06 ,  G11C11/4094 ,  G11C5/02 ,  G11C11/403 ,  G11C11/4097 ,  G11C11/4076 ,  G11C7/10 ,  G11C5/04

    Abstract: A memory device includes an array of 2T1C DRAM cells and a memory controller. The DRAM cells are arranged as a plurality of rows and columns of DRAM cells. The memory controller is internal to the memory device and is coupled to the array of DRAM cells. The memory controller is capable of receiving commands input to the memory device and is responsive to the received commands to control row-major access and column-major access to the array of DRAM cells. In one embodiment, each transistor of a memory cell includes a terminal directly coupled to a storage node of the capacitor. In another embodiment, a first transistor of a memory cell includes a terminal directly coupled to a storage node of the capacitor, and a second transistor of the 2T1C memory cell includes a gate terminal directly coupled to the storage node of the capacitor.

    Bandwidth boosted stacked memory
    86.
    发明授权
    Bandwidth boosted stacked memory 有权

    公开(公告)号：US11513965B2

    公开(公告)日：2022-11-29

    申请号：US17156362

    申请日：2021-01-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Krishna T. Malladi ,  Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng

    IPC: G06F12/08 ,  G06F12/0879 ,  G11C11/417

    Abstract: A high bandwidth memory system. In some embodiments, the system includes: a memory stack having a plurality of memory dies and eight 128-bit channels; and a logic die, the memory dies being stacked on, and connected to, the logic die; wherein the logic die may be configured to operate a first channel of the 128-bit channels in: a first mode, in which a first 64 bits operate in pseudo-channel mode, and a second 64 bits operate as two 32-bit fine-grain channels, or a second mode, in which the first 64 bits operate as two 32-bit fine-grain channels, and the second 64 bits operate as two 32-bit fine-grain channels.

    Systems and methods for write and flush support in hybrid memory
    87.
    发明授权
    Systems and methods for write and flush support in hybrid memory 有权

    公开(公告)号：US11175853B2

    公开(公告)日：2021-11-16

    申请号：US15669851

    申请日：2017-08-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Heehyun Nam ,  Youngjin Cho ,  Sun-Young Lim

    IPC: G06F3/00 ,  G06F12/00 ,  G06F3/06 ,  G06F12/0895 ,  G06F12/0868 ,  G06F13/16 ,  G06F12/02

    Abstract: A memory module includes a memory controller including: a host layer; a media layer coupled to a non-volatile memory; and a logic core coupled to the host layer, the media layer, and a volatile memory, the logic core storing a first write group table including a plurality of rows, and the logic core being configured to: receive a persistent write command including a cache line address and a write group identifier; receive data associated with the persistent write command; write the data to the volatile memory at the cache line address; store the cache line address in a selected buffer of a plurality of buffers in a second write group table, the selected buffer corresponding to the write group identifier; and update a row of the first write group table to identify locations of the selected buffer containing valid entries, the row corresponding to the write group identifier.

    Dataflow accelerator architecture for general matrix-matrix multiplication and tensor computation in deep learning
    88.
    发明授权
    Dataflow accelerator architecture for general matrix-matrix multiplication and tensor computation in deep learning 有权

    公开(公告)号：US11100193B2

    公开(公告)日：2021-08-24

    申请号：US16388860

    申请日：2019-04-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Peng Gu ,  Krishna Malladi ,  Hongzhong Zheng ,  Dimin Niu

    IPC: G06F17/16 ,  G06F12/0877 ,  G06F12/0802 ,  G06N3/063 ,  G06N3/00 ,  G06N3/04 ,  G06N3/08

    Abstract: A general matrix-matrix multiplication (GEMM) dataflow accelerator circuit is disclosed that includes a smart 3D stacking DRAM architecture. The accelerator circuit includes a memory bank, a peripheral lookup table stored in the memory bank, and a first vector buffer to store a first vector that is used as a row address into the lookup table. The circuit includes a second vector buffer to store a second vector that is used as a column address into the lookup table, and lookup table buffers to receive and store lookup table entries from the lookup table. The circuit further includes adders to sum the first product and a second product, and an output buffer to store the sum. The lookup table buffers determine a product of the first vector and the second vector without performing a multiply operation. The embodiments include a hierarchical lookup architecture to reduce latency. Accumulation results are propagated in a systolic manner.

    ADAPTIVE MATRIX MULTIPLICATION ACCELERATOR FOR MACHINE LEARNING AND DEEP LEARNING APPLICATIONS
    90.
    发明申请
    ADAPTIVE MATRIX MULTIPLICATION ACCELERATOR FOR MACHINE LEARNING AND DEEP LEARNING APPLICATIONS 审中-公开

    公开(公告)号：US20200272479A1

    公开(公告)日：2020-08-27

    申请号：US16407064

    申请日：2019-05-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongyan Jiang ,  Dimin Niu ,  Hongzhong Zheng

    IPC: G06F9/38 ,  G06F9/50 ,  G06F17/16

    Abstract: An adaptive matrix multiplier. In some embodiments, the matrix multiplier includes a first multiplying unit a second multiplying unit, a memory load circuit, and an outer buffer circuit. The first multiplying unit includes a first inner buffer circuit and a second inner buffer circuit, and the second multiplying unit includes a first inner buffer circuit and a second inner buffer circuit. The memory load circuit is configured to load data from memory, in a single burst of a burst memory access mode, into the first inner buffer circuit of the first multiplying unit; and into the first inner buffer circuit of the second multiplying unit.

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