公开(公告)号：US09716182B2

公开(公告)日：2017-07-25

申请号：US14823044

申请日：2015-08-11

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Daisuke Matsubayashi ,  Hiroyuki Miyake

IPC: H01L29/00 ,  H01L29/786 ,  H01L29/24 ,  H01L29/04 ,  H01L29/423 ,  H01L29/51 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L29/045 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78627 ,  H01L29/78696

Abstract: A highly reliable semiconductor device is provided. The semiconductor device includes a gate electrode, a gate insulating film over the gate electrode, a semiconductor film overlapping with the gate electrode with the gate insulating film positioned therebetween, a source electrode and a drain electrode that are in contact with the semiconductor film, and an oxide film over the semiconductor film, the source electrode, and the drain electrode. An end portion of the semiconductor film is spaced from an end portion of the source electrode or the drain electrode in a region overlapping with the semiconductor film in a channel width direction. The semiconductor film and the oxide film each include a metal oxide including In, Ga, and Zn. The oxide film has an atomic ratio where the atomic percent of In is lower than the atomic percent of In in the atomic ratio of the semiconductor film.

公开(公告)号：US09666722B2

公开(公告)日：2017-05-30

申请号：US14603632

申请日：2015-01-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daisuke Matsubayashi ,  Yoshiyuki Kobayashi ,  Shuhei Nagatsuka ,  Yutaka Shionoiri

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/78648 ,  H01L29/78696

Abstract: A transistor having favorable electrical characteristics. A transistor suitable for miniaturization. A transistor having a high switching speed. One embodiment of the present invention is a semiconductor device that includes a transistor. The transistor includes an oxide semiconductor, a gate electrode, and a gate insulator. The oxide semiconductor includes a first region in which the oxide semiconductor and the gate electrode overlap with each other with the gate insulator positioned therebetween. The transistor has a threshold voltage higher than 0 V and a switching speed lower than 100 nanoseconds.

公开(公告)号：US09627386B2

公开(公告)日：2017-04-18

申请号：US15193189

申请日：2016-06-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daisuke Matsubayashi

IPC: G11C8/00 ,  H01L27/105 ,  H01L27/06 ,  H01L27/1156 ,  H01L27/12 ,  G11C8/10 ,  G11C11/404 ,  G11C11/405 ,  H01L23/528 ,  H01L29/786

CPC classification number: H01L27/1052 ,  G11C8/10 ,  G11C11/404 ,  G11C11/405 ,  H01L23/528 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/7869

Abstract: A selection operation is performed for individual memory cells. A device includes a first memory cell and a second memory cell provided in the same row as the first memory cell, each of which includes a field-effect transistor having a first gate and a second gate. The field-effect transistor controls at least data writing and data holding in the memory cell by being turned on or off. The device further includes a row selection line electrically connected to the first gates of the field-effect transistors included in the first memory cell and the second memory cell, a first column selection line electrically connected to the second gate of the field-effect transistor included in the first memory cell, and a second column selection line electrically connected to the second gate of the field-effect transistor included in the second memory cell.

公开(公告)号：US09530892B2

公开(公告)日：2016-12-27

申请号：US14062481

申请日：2013-10-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Junichi Koezuka ,  Yukinori Shima ,  Hajime Tokunaga ,  Toshinari Sasaki ,  Keisuke Murayama ,  Daisuke Matsubayashi

IPC: H01L21/00 ,  H01L27/146 ,  H01L29/786 ,  H01L21/02 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78606 ,  H01L21/02109 ,  H01L21/02263 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L27/3262 ,  H01L29/51 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device includes a transistor including a gate electrode over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, and an oxide insulating film covering the transistor. The multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the oxide insulating film contains more oxygen than that in the stoichiometric composition, and in the transistor, by a bias-temperature stress test, threshold voltage does not change or the amount of the change in a positive direction or a negative direction is less than or equal to 1.0 V, preferably less than or equal to 0.5 V.

Abstract translation: 半导体器件包括晶体管，其包括在衬底上的栅电极，覆盖栅电极的栅极绝缘膜，与栅电极重叠的多层膜，其间设置有栅极绝缘膜，以及与多层膜接触的一对电极 和覆盖晶体管的氧化物绝缘膜。 多层膜包括氧化物半导体膜和含有In或Ga的氧化物膜，氧化物绝缘膜含有比化学计量组成中的氧更多的氧，并且在晶体管中，通过偏置 - 温度应力测试，阈值电压不变， 正方向或负方向的变化量小于或等于1.0V，优选小于或等于0.5V。

公开(公告)号：US09496409B2

公开(公告)日：2016-11-15

申请号：US14220544

申请日：2014-03-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Daisuke Matsubayashi

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/441 ,  H01L29/78648 ,  H01L29/7869

Abstract: A first source electrode is formed in contact with a semiconductor layer; a first drain electrode is formed in contact with the semiconductor layer; a second source electrode which extends beyond an end portion of the first source electrode to be in contact with the semiconductor layer is formed; a second drain electrode which extends beyond an end portion of the first drain electrode to be in contact with the semiconductor layer is formed; a first sidewall is formed in contact with a side surface of the second source electrode and the semiconductor layer; a second sidewall is formed in contact with a side surface of the second drain electrode and the semiconductor layer; and a gate electrode is formed to overlap the first sidewall, the second sidewall, and the semiconductor layer with a gate insulating layer provided therebetween.

Abstract translation: 第一源电极形成为与半导体层接触; 形成与半导体层接触的第一漏电极; 形成第二源电极，其延伸超过第一源电极的与半导体层接触的端部; 形成第二漏电极，其延伸超过所述第一漏电极的与所述半导体层接触的端部; 第一侧壁形成为与第二源电极和半导体层的侧表面接触; 第二侧壁形成为与第二漏电极和半导体层的侧表面接触; 并且形成栅电极以与第一侧壁，第二侧壁和半导体层重叠，其间设置有栅极绝缘层。

公开(公告)号：US09449996B2

公开(公告)日：2016-09-20

申请号：US13957819

申请日：2013-08-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiroyuki Miyake ,  Hideaki Shishido ,  Jun Koyama ,  Daisuke Matsubayashi ,  Keisuke Murayama

IPC: H01L31/00 ,  H01L27/12 ,  G02F1/1362 ,  H01L27/32 ,  G02F1/1339 ,  G02F1/1345 ,  G02F1/1343

CPC classification number: H01L27/1255 ,  G02F1/1339 ,  G02F1/134363 ,  G02F1/13454 ,  G02F1/13458 ,  G02F1/136204 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134372 ,  G02F2201/121 ,  G02F2201/123 ,  G02F2201/40 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3265 ,  H01L29/7869

Abstract: To provide a semiconductor device including a capacitor whose charge capacity is increased without reducing the aperture ratio. The semiconductor device includes a transistor including a light-transmitting semiconductor film, a capacitor where a dielectric film is provided between a pair of electrodes, an insulating film provided over the light-transmitting semiconductor film, and a light-transmitting conductive film provided over the insulating film. In the capacitor, a metal oxide film containing at least indium (In) or zinc (Zn) and formed on the same surface as the light-transmitting semiconductor film in the transistor serves as one electrode, the light-transmitting conductive film serves as the other electrode, and the insulating film provided over the light-transmitting semiconductor film serves as the dielectric film.

Abstract translation: 提供一种包括电容器的半导体器件，其电容量增加而不降低开口率。 半导体器件包括：晶体管，包括透光半导体膜，电容器，其中电介质膜设置在一对电极之间;绝缘膜设置在透光半导体膜上;以及透光导电膜， 绝缘膜。 在电容器中，与晶体管中的透光性半导体膜相同的表面上形成至少含有铟（In）或锌（Zn）的金属氧化物膜作为一个电极，透光性导电膜作为 设置在透光半导体膜上的绝缘膜用作电介质膜。

公开(公告)号：US09401432B2

公开(公告)日：2016-07-26

申请号：US14593227

申请日：2015-01-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki Kobayashi ,  Daisuke Matsubayashi

IPC: H01L29/12 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78696 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7869

Abstract: A semiconductor device of one embodiment of the present invention includes a semiconductor, an insulator, a first conductor, and a second conductor. In the semiconductor device, a top surface of the semiconductor has a region in contact with the insulator; a side surface of the semiconductor has a region in contact with the insulator; the first conductor has a first region overlapping with the semiconductor with the insulator positioned therebetween; the first region has a region in contact with the top surface of the semiconductor and a region in contact with the side surface of the semiconductor; the second conductor has a second region in contact with the semiconductor; and the first region and the second region do not overlap with each other.

Abstract translation: 本发明的一个实施例的半导体器件包括半导体，绝缘体，第一导体和第二导体。 在半导体器件中，半导体的顶表面具有与绝缘体接触的区域; 半导体的侧面具有与绝缘体接触的区域; 第一导体具有与半导体重叠的第一区域，绝缘体位于它们之间; 第一区域具有与半导体的顶表面接触的区域和与半导体的侧表面接触的区域; 所述第二导体具有与所述半导体接触的第二区域; 并且第一区域和第二区域彼此不重叠。

公开(公告)号：US09385128B2

公开(公告)日：2016-07-05

申请号：US14297668

申请日：2014-06-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daisuke Matsubayashi

IPC: G11C8/00 ,  H01L27/105 ,  H01L27/06 ,  H01L27/115 ,  G11C8/10 ,  G11C11/404 ,  G11C11/405 ,  H01L27/12

CPC classification number: H01L27/1052 ,  G11C8/10 ,  G11C11/404 ,  G11C11/405 ,  H01L23/528 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/7869

Abstract: A selection operation is performed for individual memory cells. A device includes a first memory cell and a second memory cell provided in the same row as the first memory cell, each of which includes a field-effect transistor having a first gate and a second gate. The field-effect transistor controls at least data writing and data holding in the memory cell by being turned on or off. The device further includes a row selection line electrically connected to the first gates of the field-effect transistors included in the first memory cell and the second memory cell, a first column selection line electrically connected to the second gate of the field-effect transistor included in the first memory cell, and a second column selection line electrically connected to the second gate of the field-effect transistor included in the second memory cell.

Abstract translation: 对各个存储单元执行选择操作。 一种器件包括与第一存储器单元相同的行中提供的第一存储单元和第二存储单元，每个存储单元包括具有第一栅极和第二栅极的场效应晶体管。 场效应晶体管通过导通或截止来控制存储单元中的至少数据写入和数据保持。 该装置还包括电连接到包括在第一存储单元和第二存储单元中的场效应晶体管的第一栅极的行选择线，电连接到场效应晶体管的第二栅极的第一列选择线 以及与第二存储单元中包含的场效应晶体管的第二栅极电连接的第二列选择线。

公开(公告)号：US20150171222A1

公开(公告)日：2015-06-18

申请号：US14571993

申请日：2014-12-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya Sasagawa ,  Motomu Kurata ,  Kazuya Hanaoka ,  Yoshiyuki Kobayashi ,  Daisuke Matsubayashi

IPC: H01L29/786 ,  H01L29/04

CPC classification number: H01L29/78696 ,  H01L29/045 ,  H01L29/24 ,  H01L29/7869

Abstract: A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a source electrode layer and a drain electrode layer electrically connected to the semiconductor layer, a gate insulating film over the semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer overlapping with part of the semiconductor layer, part of the source electrode layer, and part of the drain electrode layer with the gate insulating film therebetween. A cross section of the semiconductor layer in the channel width direction is substantially triangular or substantially trapezoidal. The effective channel width is shorter than that for a rectangular cross section.

Abstract translation: 提供了具有良好电气特性的半导体器件。 半导体器件包括绝缘层，绝缘层上的半导体层，与半导体层电连接的源极电极层和漏极电极层，半导体层上的栅极绝缘膜，源极电极层和漏极电极 以及与半导体层的一部分，源极电极层的一部分以及其间具有栅极绝缘膜的漏极电极层的一部分重叠的栅极电极层。 半导体层在沟道宽度方向上的截面基本上是三角形或大致梯形。 有效通道宽度短于矩形截面的宽度。

公开(公告)号：US08963148B2

公开(公告)日：2015-02-24

申请号：US14079694

申请日：2013-11-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daisuke Matsubayashi ,  Satoshi Shinohara ,  Wataru Sekine ,  Naoto Kusumoto

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/78645 ,  H01L29/78648

Abstract: Provided is a semiconductor device having a structure which can suppress a decrease in electrical characteristics, which becomes more significant with miniaturization. The semiconductor device includes a plurality of gate electrode layers separated from each other. One of the plurality of gate electrode layers includes a region which overlaps with a part of an oxide semiconductor layer, a part of a source electrode layer, and a part of a drain electrode layer. Another of the plurality of gate electrode layers overlaps with a part of an end portion of the oxide semiconductor layer. The length in the channel width direction of each of the source electrode layer and the drain electrode layer is shorter than that of the one of the plurality of gate electrode layers.

Abstract translation: 提供一种能够抑制电特性降低的结构的半导体器件，其在小型化时变得更加显着。 半导体器件包括彼此分离的多个栅极电极层。 多个栅电极层中的一个包括与氧化物半导体层的一部分，源电极层的一部分和漏电极层的一部分重叠的区域。 多个栅电极层中的另一个与氧化物半导体层的端部的一部分重叠。 源极电极层和漏极电极层的沟道宽度方向的长度比多个栅极电极层的长度短。