公开(公告)号：US10304815B2

公开(公告)日：2019-05-28

申请号：US15802541

申请日：2017-11-03

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L25/18 ,  H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48 ,  H01L23/13 ,  H01L23/15

Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip.

公开(公告)号：US10256351B2

公开(公告)日：2019-04-09

申请号：US15723149

申请日：2017-10-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/00 ,  H01L29/788 ,  H01L21/02

Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

公开(公告)号：US10249568B2

公开(公告)日：2019-04-02

申请号：US15967336

申请日：2018-04-30

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L23/528 ,  H01L49/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/06 ,  H01L27/08

Abstract: A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.

公开(公告)号：US20190051722A1

公开(公告)日：2019-02-14

申请号：US16164481

申请日：2018-10-18

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L49/02 ,  H01L27/11507 ,  H01L21/02 ,  H01L27/108 ,  H01L21/28

Abstract: An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.

公开(公告)号：US10199505B2

公开(公告)日：2019-02-05

申请号：US15620444

申请日：2017-06-12

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/778 ,  H01L29/41 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/165

Abstract: Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.

公开(公告)号：US10128327B2

公开(公告)日：2018-11-13

申请号：US14266384

申请日：2014-04-30

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L49/02 ,  H01L27/108 ,  H01L27/115 ,  H01L21/28 ,  H01L21/02 ,  H01L27/11507

Abstract: An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.

公开(公告)号：US09947772B2

公开(公告)日：2018-04-17

申请号：US14231466

申请日：2014-03-31

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/66795 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/7845 ,  H01L29/785

Abstract: Stress is introduced into the channel of an SOI FinFET device by transfer directly from a metal gate. In SOI devices in particular, stress transfer efficiency from the metal gate to the channel is nearly 100%. Either tensile or compressive stress can be applied to the fin channel by choosing different materials to be used in the gate stack as the bulk gate material, a gate liner, or a work function material, or by varying processing parameters during deposition of the gate or work function materials. P-gates and N-gates are therefore formed separately. Gate materials suitable for use as stressors include tungsten (W) for NFETs and titanium nitride (TiN) for PFETs. An optical planarization material assists in patterning the stress-inducing metal gates. A simplified process flow is disclosed in which isolation regions are formed without need for a separate mask layer, and gate sidewall spacers are not used.

公开(公告)号：US09759861B2

公开(公告)日：2017-09-12

申请号：US14983078

申请日：2015-12-29

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L21/4763 ,  G02B6/122 ,  H01L23/522 ,  G02B6/13 ,  H01L21/768 ,  H01L23/532 ,  H01L21/66 ,  G02B6/12

CPC classification number: G02B6/132 ,  G02B6/122 ,  G02B6/1225 ,  G02B6/13 ,  G02B6/136 ,  G02B2006/121 ,  H01L21/76802 ,  H01L21/76879 ,  H01L21/76883 ,  H01L22/12 ,  H01L22/14 ,  H01L23/522 ,  H01L23/53209 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths can be created substantially simultaneously in the same masking cycle. This is made possible by a disparity in the widths of the respective features, the optical signal paths being significantly wider than the electrical ones. Using a damascene process, the structures of disparate widths are plated with metal that over-fills narrow trenches and under-fills a wide trench. An optical cladding material can then be deposited into the trench so as to surround an optical core for light transmission.

公开(公告)号：US20170236826A1

公开(公告)日：2017-08-17

申请号：US15586195

申请日：2017-05-03

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L27/11 ,  H01L21/266 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L21/266 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/11213 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7838 ,  H01L29/7849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

公开(公告)号：US09730596B2

公开(公告)日：2017-08-15

申请号：US13931138

申请日：2013-06-28

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: A61B5/04 ,  A61B5/00 ,  A61N1/00 ,  G01N27/414 ,  B82Y30/00

CPC classification number: A61B5/04001 ,  A61B5/6877 ,  A61B5/688 ,  B82Y30/00 ,  G01N27/4145 ,  Y10T29/4913

Abstract: It is recognized that, because of its unique properties, graphene can serve as an interface with biological cells that communicate by an electrical impulse, or action potential. Responding to a sensed signal can be accomplished by coupling a graphene sensor to a low power digital electronic switch that is activatable by the sensed low power electrical signals. It is further recognized that low power devices such as tunneling diodes and TFETs are suitable for use in such biological applications in conjunction with graphene sensors. While tunneling diodes can be used in diagnostic applications, TFETs, which are three-terminal devices, further permit controlling the voltage on one cell according to signals received by other cells. Thus, by the use of a biological sensor system that includes graphene nanowire sensors coupled to a TFET, charge can be redistributed among different biological cells, potentially with therapeutic effects.