公开(公告)号：US20190188179A1

公开(公告)日：2019-06-20

申请号：US16204660

申请日：2018-11-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Chama Ameziane El Hassani

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/0016 ,  H03K5/1252

Abstract: In an embodiment, an electronic device for filtering an incoming digital signal includes several elementary filtering modules that include an elementary input configured to receive an incident elementary signal extracted from an incoming signal, an elementary output, and a dedicated capacitive circuit. The device further includes a resistive circuit common to all the elementary filtering modules and configured for cooperating with the capacitive circuit of each elementary filtering module in such a manner as to filter, on the respective elementary output, pulses of the incident elementary signal having a first voltage level and a duration less than a time constant and to deliver a filtered elementary signal on the elementary output.

公开(公告)号：US20190058034A1

公开(公告)日：2019-02-21

申请号：US16059654

申请日：2018-08-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: H01L29/06 ,  H01L27/088

Abstract: An electronic chip includes first transistors connected in parallel so that gates of the first transistors are interconnected, drain areas of the first transistors are interconnected, and source areas of the first transistors are interconnected. The first transistors are separated from one another by first isolating trenches. The chip also includes second transistors and second isolating trenches. The second transistors are separated from one another by the second isolating trenches. The first isolating trenches have a maximum width that is smaller than a maximum width of all the second isolating trenches.

公开(公告)号：US20190057748A1

公开(公告)日：2019-02-21

申请号：US16043218

申请日：2018-07-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/30 ,  G11C16/24

Abstract: In an embodiment, a method is provided for controlling a level of a read current in a non-volatile memory that is powered by a supply voltage includes. A model current representative of an actual current able to flow during a readout through a read path of the memory is determined based on the value of the supply voltage. The model current is compared to a reference current having a reference value. A control signal is generated. The control signal is to control the generation of the read current having a level equal to the lowest value between a fraction of the value of the model current and the reference value.

公开(公告)号：US20180322086A1

公开(公告)日：2018-11-08

申请号：US15902473

申请日：2018-02-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Chama Ameziane El Hassani

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/40 ,  H03K19/00

Abstract: In some embodiments, a buffer stage device includes a data input for receiving a data signal, a clock input for receiving a clock signal, a data output and a processor that is configured to deliver, to the data output, the data from the data signal in synchronism with clock cycles of the clock signal. The processor includes a first buffer module configured to deliver, to the data output, each datum in synchronism with a first edge of the clock signal and during a first half of a clock cycle, and a second buffer module configured to hold the datum at the data output during the second half of the clock cycle.

公开(公告)号：US20180301196A1

公开(公告)日：2018-10-18

申请号：US15842586

申请日：2017-12-14

Applicant: STMicroelectronics (Rousset)SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C16/20 ,  G06F12/02 ,  G11C16/12 ,  G11C16/10 ,  G11C11/56

Abstract: Some embodiments include a method for addressing an integrated circuit for a non-volatile memory of the EEPROM type on a bus of the I2C type. The memory includes J hardware-identification pins, with J being an integer lying between 1 and 3, which are assigned respective potentials defining an assignment code on J bits. The method includes a first mode of addressing used selectively when the assignment code is equal to a fixed reference code on J bits, and a second mode of addressing used selectively when the assignment code is different from the reference code. In the first mode, the memory plane of the non-volatile memory is addressed by a memory address contained in the last low-order bits of the slave address and in the first N bytes received. In the second mode, the memory plane is addressed by a memory address contained in the first N+1 bytes received.

公开(公告)号：US10068644B2

公开(公告)日：2018-09-04

申请号：US15054015

申请日：2016-02-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C13/00

Abstract: A method of controlling a cycle for writing at least one data item to at least one memory slot of the electrically programmable and erasable read-only memory type disposed in an electronic circuit supplied by a supply voltage includes a controlled increase of the duration of the write cycle in the presence of a decrease in the supply voltage.

公开(公告)号：US09978452B2

公开(公告)日：2018-05-22

申请号：US15682102

申请日：2017-08-21

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: G11C16/04 ,  H01L27/11526 ,  H01L29/788 ,  G11C16/14 ,  G11C16/10 ,  H01L27/11521

CPC classification number: G11C16/0408 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/7883

Abstract: A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.

公开(公告)号：US09899090B2

公开(公告)日：2018-02-20

申请号：US15608770

申请日：2017-05-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: G11C11/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/12 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C16/102 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3481 ,  G11C16/3495 ,  G11C2211/5622 ,  G11C2211/5624 ,  G11C2211/5632

Abstract: During a phase of programming the cell, a first voltage is applied to the source region and a second voltage, higher than the first voltage, is applied to the drain region until the cell is put into conduction. The numerical value of the item of data to be written is controlled by the level of the control voltage applied to the control gate and the item of data is de facto written with the numerical value during the putting into conduction of the cell. The programming is then stopped.

公开(公告)号：US20170373001A1

公开(公告)日：2017-12-28

申请号：US15380894

申请日：2016-12-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Guilhem Bouton

IPC: H01L23/522 ,  H01L27/02 ,  H01L23/528 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L21/76895 ,  H01L22/22 ,  H01L22/32 ,  H01L23/528 ,  H01L27/0207 ,  H01L28/60

Abstract: A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components according to their position in test semiconductor wafers; associating, with each component of each chip, auxiliary correction elements; activating by masking the connection of the correction elements to each component according to the initial mapping.

公开(公告)号：US09779825B2

公开(公告)日：2017-10-03

申请号：US15183515

申请日：2016-06-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista ,  Victorien Brecte

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24

CPC classification number: G11C16/26 ,  G11C7/067 ,  G11C16/0433 ,  G11C16/24

Abstract: One embodiment provides a method for reading a memory cell of a memory plane of a memory of the erasable electrically-programmable ROM type. The word line and of the bit line to which the memory cell belongs are selected and the content of the cell is read via a read amplifier. One input of the read amplifier is connected to the bit line and pre-charged at a pre-charge voltage. During the read operation, a source voltage higher than the pre-charge voltage is applied to the source of the floating-gate transistor of the cell. A read current flows from the cell towards the input of the read amplifier and then flows through a programmed cell.