公开(公告)号：US20190355727A1

公开(公告)日：2019-11-21

申请号：US16242127

申请日：2019-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Keunnam Kim ,  Eun A Kim ,  Eunjung Kim ,  Jeongseop Shim

IPC: H01L27/108 ,  H01L27/22 ,  H01L27/24 ,  H01L21/28 ,  H01L21/306 ,  H01L21/308 ,  H01L29/423

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises forming an active structure including a plurality of active patterns, a device isolation layer defining the active patterns, and a gate structure across the active patterns and extending in a first direction, forming a first mask pattern on the active structure, and forming a trench by using the first mask pattern as an etching mask to pattern the active structure. Forming the first mask pattern comprises forming in a first mask layer a plurality of first openings extending in a second direction intersecting the first direction, and forming in the first mask layer a plurality of second openings extending in a third direction intersecting the first and second directions.

公开(公告)号：US10332890B2

公开(公告)日：2019-06-25

申请号：US15653198

申请日：2017-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok Lee ,  Chan-Sic Yoon ,  Augustin Hong ,  Keunnam Kim ,  Dongoh Kim ,  Bong-Soo Kim ,  Jemin Park ,  Hoin Lee ,  Sungho Jang ,  Kiwook Jung ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L27/24 ,  H01L27/22

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

公开(公告)号：US10312105B2

公开(公告)日：2019-06-04

申请号：US15598861

申请日：2017-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-Sic Yoon ,  Jiung Pak ,  Kiseok Lee ,  Chan Ho Park ,  Hyeonok Jung

IPC: H01L21/308 ,  H01L27/108

Abstract: A method of fabricating a semiconductor device includes forming a linear preliminary mask pattern in a first direction on a substrate. The preliminary mask pattern is patterned to provide a plurality of mask patterns that are aligned end-to-end with one another on the substrate and are separated by an exposed portion of the substrate between respective facing ends of the plurality of mask patterns. An auxiliary layer is formed to cover at least sidewalls of the facing ends to reduce a size of the exposed portion to provide a reduced exposed portion of the substrate and the reduced exposed portion of the substrate is etched to form a trench defining active patterns in the substrate aligned end-to-end with one another.

公开(公告)号：US20250071967A1

公开(公告)日：2025-02-27

申请号：US18673537

申请日：2024-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyun Park ,  Inwoo Kim ,  Kiseok Lee

IPC: H10B12/00

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of contact plugs spaced apart from each other on the semiconductor substrate, a plurality of first landing pads spaced apart from each other on the plurality of contact plugs, a landing insulating layer surrounding upper sidewalls of the plurality of first landing pads and covering upper portions of the plurality of first landing pads, a stopper insulating layer disposed on the landing insulating layer, and a plurality of second landing pads spaced apart from each other on the plurality of first landing pads, passing through the stopper insulating layer, and buried in landing opening holes formed in the landing insulating layer, the plurality of second landing pads being electrically and respectively connected to the plurality of first landing pads.

公开(公告)号：US20240306379A1

公开(公告)日：2024-09-12

申请号：US18369248

申请日：2023-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHAN-SIC YOON ,  Jongmin Kim ,  Kiseok Lee

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor device including: a substrate that includes a cell region and a peripheral region, wherein the cell region includes a cell active pattern; a cell gate structure on the cell active pattern; a bit-line structure electrically connected to the cell active pattern; a peripheral gate structure on the peripheral region; a peripheral etch stop layer on the peripheral gate structure; and a cover dielectric layer on the peripheral etch stop layer, wherein the bit-line structure includes: a bit-line conductive layer; a bit-line dielectric layer on the bit-line conductive layer; a cell etch stop layer on the bit-line dielectric layer; and a bit-line capping layer on the cell etch stop layer, wherein the peripheral gate structure includes: a peripheral gate conductive layer; and a peripheral gate capping layer on the peripheral gate conductive layer.

公开(公告)号：US20240306374A1

公开(公告)日：2024-09-12

申请号：US18414655

申请日：2024-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KEUNNAM KIM ,  Seungbo Ko ,  Jongmin Kim ,  Huijung Kim ,  Sangjae Park ,  Taejin Park ,  Chansic Yoon ,  Kiseok Lee ,  Myeongdong Lee

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/0335 ,  H10B12/315

Abstract: A semiconductor device includes an active pattern array including active patterns, an isolation pattern, gate structures, bit line structures, and lower and upper contact plugs. The isolation pattern covers sidewalls of the active patterns. The gate structures extend through upper portions of the active patterns and the isolation pattern in a first direction, and are spaced apart from each other in a second direction. The bit line structures are on central portions of the active patterns and the isolation pattern, extend in the second direction, and are spaced apart from each other in the first direction. The lower contact plugs are disposed on end portions of the active patterns. The upper contact plugs are disposed on the lower contact plugs. The active pattern array includes active pattern rows including the active patterns spaced apart from each other in the first direction.

公开(公告)号：US12048141B2

公开(公告)日：2024-07-23

申请号：US17574666

申请日：2022-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok Lee ,  Hui-Jung Kim ,  Min Hee Cho

IPC: H10B12/00 ,  H01L29/786

CPC classification number: H10B12/30 ,  H01L29/78693 ,  H10B12/03 ,  H10B12/05 ,  H10B12/50

Abstract: A semiconductor memory device including: a stack structure including a plurality of layers that are vertically stacked on a substrate, each of the plurality of layers including a word line, a channel layer, and a data storage element electrically connected to the channel layer; and a bit line that vertically extends on one side of the stack structure, wherein the word line includes: a first conductive line that extends in a first direction; and a gate electrode that protrudes in a second direction from the first conductive line, the second direction intersecting the first direction, wherein the channel layer is on the gate electrode, and wherein the bit line includes a connection part electrically connected to the channel layer.

公开(公告)号：US20240032286A1

公开(公告)日：2024-01-25

申请号：US18335186

申请日：2023-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chansic Yoon ,  Jongmin Kim ,  Kiseok Lee ,  Junhyeok Ahn

IPC: H10B12/00 ,  H01L29/423

CPC classification number: H10B12/488 ,  H10B12/315 ,  H10B12/485 ,  H10B12/482 ,  H01L29/42356

Abstract: Provided is an integrated circuit device including a substrate that includes an active region defined by a trench isolation, a word line that extends in a first horizontal direction inside the substrate across the active region, a bit line that extends on the word line in a second horizontal direction orthogonal to the first horizontal direction, a direct contact that electrically connects the bit line to the active region, a pad that is on the active region and has a horizontal width that is greater than that of the active region, a buried contact that contacts a sidewall of the pad, and a conductive landing pad that extends on the buried contact in a vertical direction and faces the bit line in the first horizontal direction.

公开(公告)号：US20230402299A1

公开(公告)日：2023-12-14

申请号：US18200619

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyojin Park ,  Songyun Kang ,  Sungyong Park ,  Kiseok Lee

IPC: H01L21/67 ,  B08B1/04 ,  B08B1/00

CPC classification number: H01L21/67092 ,  B08B1/04 ,  B08B1/001

Abstract: A wafer cleaning apparatus includes a base, a roller installation table installed on the base, a wafer support unit disposed at the roller installation table and having a support roller for rotatably supporting an edge of a wafer, a pressing roller installed on the roller installation table and above the wafer support unit, and configured to press opposite surfaces of the wafer, and a driving unit providing a force in a direction, crossing a direction of a central axis of the pressing roller, so that a shape of the pressing roller is deformed. The pressing roller deformed by the driving unit applies a first pressure to a central portion of the wafer and a second pressure, different from the first pressure, to an edge portion of the water.

公开(公告)号：US11844212B2

公开(公告)日：2023-12-12

申请号：US17748261

申请日：2022-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Junsoo Kim ,  Hui-Jung Kim ,  Bong-Soo Kim ,  Satoru Yamada ,  Kyupil Lee ,  Sunghee Han ,  HyeongSun Hong ,  Yoosang Hwang

IPC: H10B41/27 ,  H01L23/532 ,  G11C7/18 ,  G11C8/14 ,  H10B41/35 ,  G11C11/404 ,  G11C11/4097 ,  H01L49/02

CPC classification number: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H01L23/53295 ,  H01L28/60 ,  H10B41/35 ,  G11C11/404 ,  G11C11/4097

Abstract: A semiconductor memory device includes a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also includes a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer includes semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.