-
公开(公告)号：US20190074378A1
公开(公告)日：2019-03-07
申请号：US16180210
申请日：2018-11-05
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei YAMAZAKI , Daisuke MATSUBAYASHI , Keisuke MURAYAMA
IPC: H01L29/786 , H01L29/78
Abstract: A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.
-
公开(公告)号：US20170309732A1
公开(公告)日：2017-10-26
申请号：US15492253
申请日：2017-04-20
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei YAMAZAKI , Kazutaka KURIKI , Yuji EGI , Hiromi SAWAI , Yusuke NONAKA , Noritaka ISHIHARA , Daisuke MATSUBAYASHI
IPC: H01L29/66 , H01L21/02 , H01L29/786
CPC classification number: H01L29/66969 , H01L21/02178 , H01L21/02266 , H01L21/0228 , H01L21/02337 , H01L21/0234 , H01L21/02565 , H01L27/1225 , H01L27/1259 , H01L27/1262 , H01L29/78648 , H01L29/7869 , H01L29/78693 , H01L29/78696
Abstract: Provided is a semiconductor device having favorable reliability. A manufacturing method of a semiconductor device comprising the steps of: forming a first oxide semiconductor having an island shape; forming a first conductor and a second conductor over the first oxide semiconductor; forming an oxide semiconductor film over the first oxide semiconductor, the first conductor, and the second conductor; forming a first insulating film over the oxide semiconductor film; forming a conductive film over the first insulating film; removing part of the first insulating film and part of the conductive film to form a first insulator and a third conductor; forming a second insulating film covering the first insulator and the third conductor; removing part of the oxide semiconductor film and part of the second insulating film to form a second oxide semiconductor and a second insulator and to expose a side surface of the first oxide semiconductor; forming a third insulator in contact with the side surface of the first oxide semiconductor and with a side surface of the second oxide semiconductor; forming a fourth insulator in contact with the third insulator; and performing a microwave-excited plasma treatment to the third insulator and the fourth insulator.
-
公开(公告)号：US20170243981A1
公开(公告)日：2017-08-24
申请号：US15450343
申请日：2017-03-06
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei Yamazaki , Masahiko HAYAKAWA , Shinpei MATSUDA , Daisuke MATSUBAYASHI
CPC classification number: H01L29/78648 , G02F1/1368 , H01L27/1225 , H01L27/124 , H01L27/1248 , H01L27/1255 , H01L27/3262 , H01L29/045 , H01L29/24 , H01L29/4908 , H01L29/66969 , H01L29/7869 , H01L29/78696
Abstract: Provided is a semiconductor device including a transistor having excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) or a semiconductor device including a transistor with high reliability. In the channel width direction of a channel-etched transistor in which an oxide semiconductor film is between first and second gate electrodes, the first and second gate electrodes are connected to each other through an opening portion in first and second gate insulating films. In addition, the first and second gate electrodes surround the oxide semiconductor film in a cross-section in the channel width direction, with the first gate insulating film provided between the first gate electrode and the oxide semiconductor film and the second gate insulating film provided between the second gate electrode and the oxide semiconductor film. Furthermore, the channel length of the transistor is 0.5 μm or longer and 6.5 μm or shorter.
-
公开(公告)号：US20170040424A1
公开(公告)日：2017-02-09
申请号：US15220498
申请日：2016-07-27
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Tetsuhiro TANAKA , Kazuki TANEMURA , Daisuke MATSUBAYASHI
Abstract: A miniaturized transistor with reduced parasitic capacitance and highly stable electrical characteristics is provided. High performance and high reliability of a semiconductor device including the transistor is achieved. A first conductor is formed over a substrate, a first insulator is formed over the first conductor, a layer that retains fixed charges is formed over the first insulator, a second insulator is formed over the layer that retains fixed charges, and a transistor is formed over the second insulator. Threshold voltage Vth is controlled by appropriate adjustment of the thicknesses of the first insulator, the second insulator, and the layer that retains fixed charges.
Abstract translation: 提供了具有降低的寄生电容和高度稳定的电特性的小型化晶体管。 实现了包括晶体管的半导体器件的高性能和高可靠性。 第一导体形成在衬底上，在第一导体上形成第一绝缘体，在第一绝缘体上形成保持固定电荷的层，在保持固定电荷的层上形成第二绝缘体，形成晶体管 在第二绝缘体上。 通过适当调节第一绝缘体，第二绝缘体和保持固定电荷的层的厚度来控制阈值电压Vth。
-
公开(公告)号：US20160358923A1
公开(公告)日：2016-12-08
申请号：US15240328
申请日：2016-08-18
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Daisuke MATSUBAYASHI
IPC: H01L27/108
CPC classification number: H01L27/1085 , C23C14/08 , H01L21/84 , H01L27/0688 , H01L27/105 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L27/10894 , H01L27/10897 , H01L27/115 , H01L27/11507 , H01L27/11514 , H01L27/1156 , H01L27/1203 , H01L27/1207 , H01L27/1225 , H01L27/1255 , H01L28/40 , H01L29/78642 , H01L29/7869
Abstract: A memory device that is as small in area as possible and has an extremely long data retention period. A transistor with extremely low leakage current is used as a cell transistor of a memory element in a memory device. Moreover, in order to reduce the area of a memory cell, the transistor is formed so that its source and drain are stacked in the vertical direction in a region where a bit line and a word line intersect each other. Further, a capacitor is stacked above the transistor.
Abstract translation: 一种存储器件，其面积尽可能小，数据保存期极长。 具有极低泄漏电流的晶体管被用作存储器件中的存储元件的单元晶体管。 此外，为了减小存储单元的面积，晶体管形成为使得其源极和漏极在位线和字线相交的区域中沿垂直方向堆叠。 此外，电容器堆叠在晶体管的上方。
-
Patent Agency Ranking
公开(公告)号：US20160336355A1
公开(公告)日：2016-11-17
申请号：US15223079
申请日：2016-07-29
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei YAMAZAKI , Hiroyuki MIYAKE , Hideaki SHISHIDO , Jun KOYAMA , Daisuke MATSUBAYASHI , Keisuke MURAYAMA
IPC: H01L27/12 , G02F1/1343 , G02F1/1362 , H01L29/786 , G02F1/1368
CPC classification number: H01L27/1255 , G02F1/1339 , G02F1/134363 , G02F1/13454 , G02F1/13458 , G02F1/136204 , G02F1/136209 , G02F1/136213 , G02F1/136286 , G02F1/1368 , G02F2001/134372 , G02F2201/121 , G02F2201/123 , G02F2201/40 , H01L27/1225 , H01L27/124 , H01L27/3265 , H01L29/7869
Abstract: To provide a semiconductor device including a capacitor whose charge capacity is increased without reducing the aperture ratio. The semiconductor device includes a transistor including a light-transmitting semiconductor film, a capacitor where a dielectric film is provided between a pair of electrodes, an insulating film provided over the light-transmitting semiconductor film, and a light-transmitting conductive film provided over the insulating film. In the capacitor, a metal oxide film containing at least indium (In) or zinc (Zn) and formed on the same surface as the light-transmitting semiconductor film in the transistor serves as one electrode, the light-transmitting conductive film serves as the other electrode, and the insulating film provided over the light-transmitting semiconductor film serves as the dielectric film.
Abstract translation: 提供一种包括电容器的半导体器件，其电容量增加而不降低开口率。 半导体器件包括：晶体管，包括透光半导体膜，电容器，其中电介质膜设置在一对电极之间;绝缘膜设置在透光半导体膜上;以及透光导电膜， 绝缘膜。 在电容器中，与晶体管中的透光性半导体膜相同的表面上形成至少含有铟（In）或锌（Zn）的金属氧化物膜作为一个电极，透光性导电膜作为 设置在透光半导体膜上的绝缘膜用作电介质膜。
-
公开(公告)号：US20160276372A1
公开(公告)日：2016-09-22
申请号：US15082443
申请日：2016-03-28
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei Yamazaki , Masahiko HAYAKAWA , Shinpei MATSUDA , Daisuke MATSUBAYASHI
CPC classification number: H01L29/78648 , G02F1/1368 , H01L27/1225 , H01L27/124 , H01L27/1248 , H01L27/1255 , H01L27/3262 , H01L29/045 , H01L29/24 , H01L29/4908 , H01L29/66969 , H01L29/7869 , H01L29/78696
Abstract: Provided is a semiconductor device including a transistor having excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) or a semiconductor device including a transistor with high reliability. In the channel width direction of a channel-etched transistor in which an oxide semiconductor film is between first and second gate electrodes, the first and second gate electrodes are connected to each other through an opening portion in first and second gate insulating films. In addition, the first and second gate electrodes surround the oxide semiconductor film in a cross-section in the channel width direction, with the first gate insulating film provided between the first gate electrode and the oxide semiconductor film and the second gate insulating film provided between the second gate electrode and the oxide semiconductor film. Furthermore, the channel length of the transistor is 0.5 μm or longer and 6.5 μm or shorter.
Abstract translation: 提供了包括具有优异的电特性（例如导通电流，场效应迁移率或频率特性）的晶体管或包括具有高可靠性的晶体管的半导体器件的半导体器件。 在其中氧化物半导体膜位于第一和第二栅电极之间的沟道蚀刻晶体管的沟道宽度方向上，第一和第二栅极通过第一和第二栅极绝缘膜中的开口部彼此连接。 此外，第一和第二栅电极在沟道宽度方向的横截面中包围氧化物半导体膜，第一栅极绝缘膜设置在第一栅极和氧化物半导体膜之间，第二栅极绝缘膜设置在第二栅极绝缘膜之间 第二栅电极和氧化物半导体膜。 此外，晶体管的沟道长度为0.5μm以上且6.5μm以下。
-
公开(公告)号：US20160181438A1
公开(公告)日：2016-06-23
申请号：US15057614
申请日：2016-03-01
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei Yamazaki , Daisuke MATSUBAYASHI , Yoshiyuki KOBAYASHI
IPC: H01L29/786 , H01L29/06
CPC classification number: H01L29/78693 , H01L27/1225 , H01L29/0684 , H01L29/42384 , H01L29/7869 , H01L29/78696
Abstract: A semiconductor device is provided with a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film in contact with a top surface of the insulating surface, a side surface of the first oxide semiconductor film, and side and top surfaces of the second oxide semiconductor film; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with the gate insulating film and faces the top and side surfaces a of the second oxide semiconductor film. A thickness of the first oxide semiconductor film is larger than a sum of a thickness of the third oxide semiconductor film and a thickness of the gate insulating film, and the difference is larger than or equal to 20 nm.
-
公开(公告)号：US20160071840A1
公开(公告)日：2016-03-10
申请号：US14841773
申请日：2015-09-01
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Yoshitaka YAMAMOTO , Masayuki SAKAKURA , Tetsuhiro TANAKA , Daisuke MATSUBAYASHI
IPC: H01L27/06 , H01L29/786 , H01L49/02 , H01L23/50
CPC classification number: H01L27/0688 , H01L21/8258 , H01L23/5223 , H01L27/1156 , H01L28/40 , H01L29/7869 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device that includes transistors with different threshold voltages is provided. Alternatively, a semiconductor device including a plurality of kinds of circuits and transistors whose electrical characteristics are different between the circuits is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor includes an oxide semiconductor, a conductor, a first insulator, a second insulator, and a third insulator. The conductor has a region where the conductor and the oxide semiconductor overlap with each other. The first insulator is positioned between the conductor and the oxide semiconductor. The second insulator is positioned between the conductor and the first insulator. The third insulator is positioned between the conductor and the second insulator. The second insulator has a negatively charged region.
Abstract translation: 提供了包括具有不同阈值电压的晶体管的半导体器件。 或者，提供包括电路的电特性不同的多种电路和晶体管的半导体器件。 半导体器件包括第一晶体管和第二晶体管。 第一晶体管包括氧化物半导体，导体，第一绝缘体，第二绝缘体和第三绝缘体。 导体具有导体和氧化物半导体彼此重叠的区域。 第一绝缘体位于导体和氧化物半导体之间。 第二绝缘体位于导体和第一绝缘体之间。 第三绝缘体位于导体和第二绝缘体之间。 第二绝缘体具有带负电荷的区域。
-
公开(公告)号：US20160035897A1
公开(公告)日：2016-02-04
申请号：US14812028
申请日：2015-07-29
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Yoshiyuki KOBAYASHI , Shinpei MATSUDA , Daisuke MATSUBAYASHI , Hiroyuki TOMISU
IPC: H01L29/786 , H01L29/04 , H01L29/24
CPC classification number: H01L29/7869 , G02F1/1368 , G02F2201/58 , H01L21/8221 , H01L27/0688 , H01L29/045 , H01L29/78696
Abstract: A transistor whose channel is formed in a semiconductor having dielectric anisotropy is provided. A transistor having a small subthreshold swing value is provided. A transistor having normally-off electrical characteristics is provided. A transistor having a low leakage current in an off state is provided. A semiconductor device includes an insulator, a semiconductor, and a conductor. In the semiconductor device, the semiconductor includes a region overlapping with the conductor with the insulator positioned therebetween, and a dielectric constant of the region in a direction perpendicular to a top surface of the region is higher than a dielectric constant of the region in a direction parallel to the top surface.
Abstract translation: 提供其沟道形成在具有介电各向异性的半导体中的晶体管。 提供具有小的亚阈值摆动值的晶体管。 提供具有常关电特性的晶体管。 提供了处于断开状态的具有低泄漏电流的晶体管。 半导体器件包括绝缘体，半导体和导体。 在半导体器件中，半导体包括与绝缘体位于其间的与导体重叠的区域，并且该区域在与该区域的顶表面垂直的方向上的介电常数高于该区域的方向上的介电常数 平行于顶面。
-
-
-
-
-
-
-
-
-
Search Results
94
records
(took 0.049 seconds)
