公开(公告)号：US20180233597A1

公开(公告)日：2018-08-16

申请号：US15946149

申请日：2018-04-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka YAMAMOTO ,  Tetsuhiro TANAKA ,  Toshihiko TAKEUCHI ,  Yasumasa YAMANE ,  Takayuki INOUE ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L27/1156

CPC classification number: H01L29/7869 ,  H01L27/1156 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A manufacturing method of a semiconductor device in which the threshold is adjusted to an appropriate value is provided. The semiconductor device includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is sandwiched, an electron trap layer between the first gate electrode and the semiconductor, and a gate insulating layer between the second gate electrode and the semiconductor. By keeping a potential of the first gate electrode higher than a potential of the source or drain electrode for 1 second or more while heating, electrons are trapped in the electron trap layer. Consequently, threshold is increased and Icut is reduced.

公开(公告)号：US20160071840A1

公开(公告)日：2016-03-10

申请号：US14841773

申请日：2015-09-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka YAMAMOTO ,  Masayuki SAKAKURA ,  Tetsuhiro TANAKA ,  Daisuke MATSUBAYASHI

IPC: H01L27/06 ,  H01L29/786 ,  H01L49/02 ,  H01L23/50

CPC classification number: H01L27/0688 ,  H01L21/8258 ,  H01L23/5223 ,  H01L27/1156 ,  H01L28/40 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device that includes transistors with different threshold voltages is provided. Alternatively, a semiconductor device including a plurality of kinds of circuits and transistors whose electrical characteristics are different between the circuits is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor includes an oxide semiconductor, a conductor, a first insulator, a second insulator, and a third insulator. The conductor has a region where the conductor and the oxide semiconductor overlap with each other. The first insulator is positioned between the conductor and the oxide semiconductor. The second insulator is positioned between the conductor and the first insulator. The third insulator is positioned between the conductor and the second insulator. The second insulator has a negatively charged region.

Abstract translation: 提供了包括具有不同阈值电压的晶体管的半导体器件。 或者，提供包括电路的电特性不同的多种电路和晶体管的半导体器件。 半导体器件包括第一晶体管和第二晶体管。 第一晶体管包括氧化物半导体，导体，第一绝缘体，第二绝缘体和第三绝缘体。 导体具有导体和氧化物半导体彼此重叠的区域。 第一绝缘体位于导体和氧化物半导体之间。 第二绝缘体位于导体和第一绝缘体之间。 第三绝缘体位于导体和第二绝缘体之间。 第二绝缘体具有带负电荷的区域。

公开(公告)号：US20150060846A1

公开(公告)日：2015-03-05

申请号：US14471766

申请日：2014-08-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka YAMAMOTO ,  Tetsuhiro TANAKA ,  Takayuki INOUE ,  Hideomi SUZAWA

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/02 ,  H01L29/786 ,  H01L29/51

CPC classification number: H01L29/7869 ,  H01L21/0214 ,  H01L21/02181 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/28194 ,  H01L21/28282 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31645 ,  H01L21/32136 ,  H01L21/441 ,  H01L21/465 ,  H01L21/473 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78693 ,  H01L29/78696 ,  H01L29/792

Abstract: A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P≧45−0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted.

Abstract translation: 提供其中调整阈值的半导体器件。 在包括半导体，与半导体电连接的源电极或漏电极，栅电极和栅电极和半导体之间的电子捕获层的晶体管中，电子捕获层包括结晶的氧化铪。 通过使用氧化铪作为靶的溅射法沉积结晶的氧化铪。 溅射法中，衬底温度为Tsub（℃），气氛中氧的比例为P（％）时，P≥45〜0.15×Tsub。 结晶的氧化铪具有优异的电子捕获性能。 通过适当数量的电子的陷阱，可以调整半导体器件的阈值。

公开(公告)号：US20160343870A1

公开(公告)日：2016-11-24

申请号：US15230732

申请日：2016-08-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka YAMAMOTO ,  Tetsuhiro TANAKA ,  Takayuki INOUE ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/792 ,  H01L21/441 ,  H01L29/51 ,  H01L29/49 ,  H01L21/465 ,  H01L21/02 ,  H01L29/24 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/0214 ,  H01L21/02181 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/28194 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31645 ,  H01L21/32136 ,  H01L21/441 ,  H01L21/465 ,  H01L21/473 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/40117 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78693 ,  H01L29/78696 ,  H01L29/792

Abstract: A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P≧45−0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted.

公开(公告)号：US20160260835A1

公开(公告)日：2016-09-08

申请号：US15057364

申请日：2016-03-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yoshitaka YAMAMOTO

IPC: H01L29/786 ,  H01L21/477 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/477 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/0684 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78696 ,  H01L29/8611

Abstract: A transistor with favorable electrical characteristics, a transistor with stable electrical characteristics, or a highly integrated semiconductor device is provided. In a top-gate transistor in which an oxide semiconductor is used for a semiconductor layer where a channel is formed, elements are introduced to the semiconductor layer in a self-aligned manner after a gate electrode is formed. After that, a side surface of the gate electrode is covered with a structure body. The structure body preferably contains silicon oxide. A first insulating layer is formed to cover the semiconductor layer, the gate electrode, and the structure body. A second insulating layer is formed by a sputtering method over the first insulating layer. Oxygen is introduced to the first insulating layer when the second insulating layer is formed.

Abstract translation: 提供具有良好电特性的晶体管，具有稳定电特性的晶体管或高度集成的半导体器件。 在其中使用氧化物半导体用于形成沟道的半导体层的顶栅晶体管中，在形成栅电极之后，以自对准的方式将元件引入半导体层。 之后，用结构体覆盖栅电极的侧面。 结构体优选含有氧化硅。 形成第一绝缘层以覆盖半导体层，栅电极和结构体。 在第一绝缘层上通过溅射法形成第二绝缘层。 当形成第二绝缘层时，氧被引入第一绝缘层。

公开(公告)号：US20160043110A1

公开(公告)日：2016-02-11

申请号：US14817709

申请日：2015-08-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki Atsumi ,  Masayuki SAKAKURA ,  Yoshitaka YAMAMOTO ,  Jun KOYAMA ,  Tetsuhiro TANAKA ,  Kazuki TANEMURA

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L29/78648

Abstract: A highly reliable semiconductor device that is suitable for high-speed operation is provided. A semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit has an arithmetic processing function. The second circuit includes a memory circuit. The memory circuit includes a transistor which includes a first conductor, a second conductor, a first insulator, a second insulator, and a semiconductor. The first conductor includes a region overlapping the semiconductor with the first insulator positioned between the first conductor and the semiconductor. The second conductor includes a region overlapping the semiconductor with the second insulator positioned between the second conductor and the semiconductor. The first conductor is capable of selecting on or off of the transistor. The third circuit is electrically connected to the second conductor, and is capable of changing the potential of the second conductor in synchronization with an operation of the transistor.

Abstract translation: 提供了一种适用于高速运行的高度可靠的半导体器件。 半导体器件包括第一电路，第二电路和第三电路。 第一电路具有算术处理功能。 第二电路包括存储电路。 存储电路包括晶体管，其包括第一导体，第二导​​体，第一绝缘体，第二绝缘体和半导体。 第一导体包括与半导体重叠的区域和位于第一导体和半导体之间的第一绝缘体。 第二导体包括与半导体重叠的区域，位于第二导体和半导体之间的第二绝缘体。 第一导体能够选择晶体管的导通或截止。 第三电路电连接到第二导体，并且能够与晶体管的操作同步地改变第二导体的电位。

公开(公告)号：US20160267950A1

公开(公告)日：2016-09-15

申请号：US15159919

申请日：2016-05-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka YAMAMOTO ,  Kiyoshi KATO

IPC: G11C5/14 ,  H01L27/108 ,  H01L27/12 ,  H01L23/528 ,  H01L29/786 ,  G11C11/408 ,  G11C11/24 ,  H01L27/06 ,  G11C11/409 ,  H01L27/105 ,  G11C8/10 ,  G11C8/08 ,  G11C11/56 ,  H01L29/24 ,  G11C7/12

CPC classification number: G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C8/16 ,  G11C11/24 ,  G11C11/405 ,  G11C11/4087 ,  G11C11/409 ,  G11C11/565 ,  G11C2207/108 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/1082 ,  H01L27/10826 ,  H01L27/10855 ,  H01L27/10858 ,  H01L27/10873 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/786 ,  H01L29/7869

Abstract: A novel semiconductor device where multilevel data can be written and read. The semiconductor device includes first to fifth transistors, a capacitor, a bit line, and a power supply line. Write operation is performed in such a manner that first data is supplied to a gate of the fifth transistor through the first transistor; the first transistor is turned off; second data is supplied to a second electrode of the capacitor through the second transistor to convert the first data into third data; and the second electrode of the capacitor are made electrically floating. The second electrode of the capacitor is initialized to GND through the third transistor. Read operation is performed by charging or discharging the bit line through the fourth transistor and the fifth transistor. The first to third transistors are preferably oxide semiconductor transistors.

公开(公告)号：US20150008428A1

公开(公告)日：2015-01-08

申请号：US14313154

申请日：2014-06-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka YAMAMOTO ,  Tetsuhiro TANAKA ,  Toshihiko TAKEUCHI ,  Yasumasa YAMANE ,  Takayuki INOUE ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1156 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A manufacturing method of a semiconductor device in which the threshold is adjusted to an appropriate value is provided. The semiconductor device includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is sandwiched, an electron trap layer between the first gate electrode and the semiconductor, and a gate insulating layer between the second gate electrode and the semiconductor. By keeping a potential of the first gate electrode higher than a potential of the source or drain electrode for 1 second or more while heating, electrons are trapped in the electron trap layer. Consequently, threshold is increased and Icut is reduced.

Abstract translation: 提供了将阈值调整为适当值的半导体器件的制造方法。 半导体器件包括半导体，与半导体电连接的源极或漏极，第一栅电极和第二栅电极，半导体夹在其间，第一栅电极和半导体之间的电子陷阱层和栅极 第二栅电极和半导体之间的绝缘层。 通过在加热的同时保持第一栅电极的电位高于源极或漏极的电位1秒以上，电子被捕获在电子阱层中。 因此，阈值增加并且Icut减小。

公开(公告)号：US20170271521A1

公开(公告)日：2017-09-21

申请号：US15610683

申请日：2017-06-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yoshitaka YAMAMOTO

IPC: H01L29/786 ,  H01L21/477 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/477 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/0684 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78696 ,  H01L29/8611

Abstract: A transistor with favorable electrical characteristics, a transistor with stable electrical characteristics, or a highly integrated semiconductor device is provided. In a top-gate transistor in which an oxide semiconductor is used for a semiconductor layer where a channel is formed, elements are introduced to the semiconductor layer in a self-aligned manner after a gate electrode is formed. After that, a side surface of the gate electrode is covered with a structure body. The structure body preferably contains silicon oxide. A first insulating layer is formed to cover the semiconductor layer, the gate electrode, and the structure body. A second insulating layer is formed by a sputtering method over the first insulating layer. Oxygen is introduced to the first insulating layer when the second insulating layer is formed.

公开(公告)号：US20150069387A1

公开(公告)日：2015-03-12

申请号：US14479623

申请日：2014-09-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka YAMAMOTO ,  Tetsuhiro TANAKA ,  Takayuki INOUE ,  Hideomi SUZAWA ,  Yasuhiko TAKEMURA

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  G11C11/24 ,  G11C16/00 ,  G11C16/0466 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78696 ,  H01L29/7881

Abstract: A method for manufacturing a semiconductor device with adjusted threshold is provided. In a semiconductor device including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is provided, a charge trap layer provided between the first gate electrode and the semiconductor, and a gate insulating layer provided between the second gate electrode and the semiconductor, a threshold is increased by trapping electrons in the charge trap layer by keeping a potential of the first gate electrode at a potential higher than a potential of the source or drain electrode for 1 second or more while heating. After the threshold adjustment process, the first gate electrode is removed or insulated from other circuits. Alternatively, a resistor may be provided between the first gate electrode and other circuits.

Abstract translation: 提供一种用于制造具有调节阈值的半导体器件的方法。 在包括半导体，与半导体电连接的源电极或漏电极的半导体器件中，设置有半导体的第一栅电极和第二栅电极，设置在第一栅电极和半导体之间的电荷陷阱层，以及 设置在第二栅电极和半导体之间的栅极绝缘层，通过将第一栅电极的电位保持在高于源电极或漏电极的电位的电位为1，通过在电荷陷阱层中俘获电子来增加阈值 第二次或多次加热。 在阈值调整处理之后，第一栅电极被去除或与其它电路绝缘。 或者，可以在第一栅极电极和其它电路之间设置电阻器。