公开(公告)号：US20150179775A1

公开(公告)日：2015-06-25

申请号：US14626176

申请日：2015-02-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Motomu KURATA

IPC: H01L29/66 ,  H01L21/441

CPC classification number: H01L29/66969 ,  H01L21/441 ,  H01L29/41733 ,  H01L29/7869

Abstract: An object is to provide a semiconductor device in which defects are reduced and miniaturization is achieved while favorable characteristics are maintained. A semiconductor layer is formed; a first conductive layer is formed over the semiconductor layer; the first conductive layer is etched with use of a first resist mask to form a second conductive layer having a recessed portion; the first resist mask is reduced in size to form a second resist mask; the second conductive layer is etched with use of the second resist mask to form source and drain electrodes each having a projecting portion with a tapered shape at the peripheries; a gate insulating layer is formed over the source and drain electrodes to be in contact with part of the semiconductor layer; and a gate electrode is formed in a portion over the gate insulating layer and overlapping with the semiconductor layer.

Abstract translation: 本发明的目的是提供一种在保持有利特性的同时减小缺陷并实现小型化的半导体器件。 形成半导体层; 在半导体层上形成第一导电层; 使用第一抗蚀剂掩模蚀刻第一导电层以形成具有凹部的第二导电层; 第一抗蚀剂掩模的尺寸减小以形成第二抗蚀剂掩模; 使用第二抗蚀剂掩模蚀刻第二导电层，以形成在周边具有锥形形状的突出部分的源极和漏极; 在源极和漏极上形成栅极绝缘层以与半导体层的一部分接触; 并且栅极电极形成在栅极绝缘层上方并与半导体层重叠的部分。

公开(公告)号：US20150137124A1

公开(公告)日：2015-05-21

申请号：US14609814

申请日：2015-01-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuji EGI ,  Hideomi SUZAWA ,  Shinya SASAGAWA

IPC: H01L29/786 ,  H01L29/06

CPC classification number: H01L29/7869 ,  H01L21/0206 ,  H01L21/02565 ,  H01L21/44 ,  H01L21/465 ,  H01L21/4757 ,  H01L21/47635 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/127 ,  H01L27/14616 ,  H01L29/045 ,  H01L29/0684 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78693

Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.

Abstract translation: 在包括其中设置有侧壁绝缘层的侧表面上的氧化物半导体层，栅极绝缘层和栅电极层的晶体管的半导体器件中，依次层叠源电极层和漏电极层 提供与氧化物半导体层和侧壁绝缘层接触。 在制造半导体器件的方法中，层叠导电层和层间绝缘层以覆盖氧化物半导体层，侧壁绝缘层和栅极电极层。 然后，通过化学机械抛光方法去除层间绝缘层和栅电极层上的导电层的部分，从而形成源电极层和漏电极层。 在形成栅绝缘层之前，对氧化物半导体层进行清洗处理。

公开(公告)号：US20150056750A1

公开(公告)日：2015-02-26

申请号：US14527103

申请日：2014-10-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Hiroshi FUJIKI ,  Yoshinori IEDA

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/4757

CPC classification number: H01L29/66969 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/47573 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/7869

Abstract: A first insulating film in contact with an oxide semiconductor film and a second insulating film are stacked in this order over an electrode film of a transistor including the oxide semiconductor film, an etching mask is formed over the second insulating film, an opening portion exposing the electrode film is formed by etching a portion of the first insulating film and a portion of the second insulating film, the opening portion exposing the electrode film is exposed to argon plasma, the etching mask is removed, and a conductive film is formed in the opening portion exposing the electrode film. The first insulating film is an insulating film whose oxygen is partly released by heating. The second insulating film is less easily etched than the first insulating film and has a lower gas-permeability than the first insulating film.

Abstract translation: 与氧化物半导体膜和第二绝缘膜接触的第一绝缘膜依次层叠在包含氧化物半导体膜的晶体管的电极膜上，在第二绝缘膜上形成蚀刻掩模， 通过蚀刻第一绝缘膜的一部分和第二绝缘膜的一部分形成电极膜，将暴露于电极膜的开口部暴露于氩等离子体中，除去蚀刻掩模，并且在开口中形成导电膜 部分暴露电极膜。 第一绝缘膜是其氧气通过加热部分释放的绝缘膜。 第二绝缘膜比第一绝缘膜不易蚀刻，并且具有比第一绝缘膜更低的透气性。

公开(公告)号：US20150041805A1

公开(公告)日：2015-02-12

申请号：US14493383

申请日：2014-09-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Motomu KURATA

IPC: H01L29/786 ,  H01L29/423

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02581 ,  H01L21/02631 ,  H01L21/34 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/78618

Abstract: Provided is a miniaturized transistor having high electrical characteristics. The transistor includes a source electrode layer in contact with one side surface of the oxide semiconductor layer in the channel-length direction and a drain electrode layer in contact with the other side surface thereof. The transistor further includes a gate electrode layer in a region overlapping with a channel formation region with a gate insulating layer provided therebetween and a conductive layer having a function as part of the gate electrode layer in a region overlapping with the source electrode layer or the drain electrode layer with the gate insulating layer provided therebetween and in contact with a side surface of the gate electrode layer. With such a structure, an Lov region is formed with a scaled-down channel length maintained.

Abstract translation: 提供具有高电特性的小型化晶体管。 晶体管包括与沟道长度方向上的氧化物半导体层的一个侧面接触的源极电极层和与其另一个侧面接触的漏极电极层。 晶体管还包括在与沟道形成区域重叠的区域中的栅极电极层，栅极绝缘层设置在其间，并且在与源极电极层或漏极重叠的区域中具有作为栅极电极层的一部分的功能的导电层 电极层，其间设置有栅极绝缘层，并与栅电极层的侧表面接触。 利用这种结构，形成保持缩小的通道长度的Lov区域。

公开(公告)号：US20150017541A1

公开(公告)日：2015-01-15

申请号：US14472962

申请日：2014-08-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Ryota TAJIMA ,  Shunpei YAMAZAKI ,  Teppei OGUNI ,  Takeshi OSADA ,  Shinya SASAGAWA ,  Kazutaka KURIKI

IPC: H01M4/133 ,  H01M10/0525

CPC classification number: H01M4/133 ,  B82Y30/00 ,  H01M4/134 ,  H01M4/1395 ,  H01M4/366 ,  H01M4/386 ,  H01M4/625 ,  H01M10/0525 ,  H01M10/465 ,  Y02E60/122 ,  Y02T10/7011

Abstract: A power storage device which has high charge/discharge capacity and less deterioration in battery characteristics due to charge/discharge and can perform charge/discharge at high speed is provided. A power storage device includes a negative electrode. The negative electrode includes a current collector and an active material layer provided over the current collector. The active material layer includes a plurality of protrusions protruding from the current collector and a graphene provided over the plurality of protrusions. Axes of the plurality of protrusions are oriented in the same direction. A common portion may be provided between the current collector and the plurality of protrusions.

Abstract translation: 具有充电/放电容量高，蓄电池特性劣化少的蓄电装置，能够高速进行充放电。 蓄电装置包括负极。 负极包括设置在集电体上方的集电体和活性物质层。 活性物质层包括从集电体突出的多个突起和设置在多个突起上的石墨烯。 多个突起的轴线朝向相同的方向。 在集电体和多个突起之间可以设置公共部分。

公开(公告)号：US20140106504A1

公开(公告)日：2014-04-17

申请号：US14054162

申请日：2013-10-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Tetsuhiro TANAKA

IPC: H01L21/02 ,  H01L29/26 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L21/02565 ,  C23C14/086 ,  C23C14/3414 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02592 ,  H01L21/02609 ,  H01L21/02617 ,  H01L21/02631 ,  H01L21/441 ,  H01L21/47576 ,  H01L21/47635 ,  H01L29/045 ,  H01L29/26 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7869

Abstract: To provide a semiconductor device in which an increase in oxygen vacancies is suppressed. To provide a semiconductor device with favorable electrical characteristics. To provide a highly reliable semiconductor device. In a semiconductor device in which a channel formation region is included in an oxide semiconductor layer, an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer are used to supply oxygen of the gate insulating film, which is introduced by an ion implantation method, to the oxide semiconductor layer.

Abstract translation: 提供抑制氧空位增加的半导体器件。 提供具有良好电特性的半导体器件。 提供高度可靠的半导体器件。 在氧化物半导体层中包括沟道形成区域的半导体器件中，使用氧化物半导体层下方并与氧化物半导体层接触的氧化物绝缘膜和与氧化物半导体层接触并与氧化物半导体层接触的栅极绝缘膜供给氧 通过离子注入法引入的栅极绝缘膜到氧化物半导体层。

公开(公告)号：US20130161605A1

公开(公告)日：2013-06-27

申请号：US13716891

申请日：2012-12-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shinya SASAGAWA ,  Hideomi SUZAWA

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1156 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/66477 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/78606 ,  H01L29/78636 ,  H01L29/78696

Abstract: A bottom-gate transistor with a short channel length and a method for manufacturing the transistor are provided. A bottom-gate transistor with a short channel length in which portions of a source electrode and a drain electrode which are proximate to a channel formation region are thinner than other portions thereof was devised. In addition, the portions of the source electrode and the drain electrode which are proximate to the channel formation region are formed in a later step than the other portions thereof, whereby a bottom-gate transistor with a short channel length can be manufactured.

Abstract translation: 提供具有短沟道长度的底栅晶体管和制造晶体管的方法。 设计了具有短沟道长度的底栅晶体管，其中靠近沟道形成区的源电极和漏极的部分比其它部分薄。 此外，靠近沟道形成区域的源电极和漏极的部分以比其它部分稍后的步骤形成，由此可以制造具有短沟道长度的底栅晶体管。

公开(公告)号：US20130140555A1

公开(公告)日：2013-06-06

申请号：US13686332

申请日：2012-11-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Motomu KURATA ,  Shinya SASAGAWA ,  Taiga MURAOKA ,  Tetsuhiro TANAKA ,  Junichi KOEZUKA

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/66742 ,  H01L29/66969

Abstract: Provided is a miniaturized transistor with stable and high electrical characteristics with high yield. In a semiconductor device including the transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer are stacked in this order, a first sidewall insulating layer is provided in contact with a side surface of the gate electrode layer, and a second sidewall insulating layer is provided to cover a side surface of the first sidewall insulating layer. The first sidewall insulating layer is an aluminum oxide film in which a crevice with an even shape is formed on its side surface. The second sidewall insulating layer is provided to cover the crevice. A source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film and the second sidewall insulating layer.

公开(公告)号：US20130137213A1

公开(公告)日：2013-05-30

申请号：US13677663

申请日：2012-11-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuji EGI ,  Hideomi SUZAWA ,  Shinya SASAGAWA

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L21/0206 ,  H01L21/02565 ,  H01L21/44 ,  H01L21/465 ,  H01L21/4757 ,  H01L21/47635 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/127 ,  H01L27/14616 ,  H01L29/045 ,  H01L29/0684 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78693

Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.

公开(公告)号：US20250126993A1

公开(公告)日：2025-04-17

申请号：US18695175

申请日：2022-09-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shinya SASAGAWA ,  Ryota HODO ,  Kentaro SUGAYA

IPC: H10K59/131 ,  H10K59/12 ,  H10K59/122 ,  H10K59/80

Abstract: A highly reliable display device is provided. The display device includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, an insulating layer, a functional layer, and a light-emitting layer. The second conductive layer is provided over the first conductive layer and the third conductive layer is provided over the second conductive layer. A side surface of the second conductive layer is positioned on the inner side of side surfaces of the first and third conductive layers in a cross-sectional view. The insulating layer is provided to cover at least part of the side surface of the second conductive layer. The fourth conductive layer is provided to cover the first to third conductive layers and the insulating layer and to be electrically connected to the first to third conductive layers. The functional layer is provided to include a region in contact with the fourth conductive layer and the light-emitting layer is provided over the functional layer. The visible light reflectance of at least one of the first to third conductive layers is higher than the visible light reflectance of the fourth conductive layer.