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公开(公告)号：US10019355B2
公开(公告)日：2018-07-10
申请号：US15859724
申请日：2018-01-01
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Hong-Jung Hsu
CPC classification number: G06F12/0246 , G06F3/0608 , G06F3/061 , G06F3/0629 , G06F11/1072 , G06F11/108 , G06F12/0804 , G06F2212/1016 , G06F2212/1032 , G06F2212/7203 , G06F2212/7208 , G11C11/5628 , G11C16/10 , G11C16/26 , G11C2211/5641
Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
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公开(公告)号：US20180143877A1
公开(公告)日：2018-05-24
申请号：US15876211
申请日：2018-01-22
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Hong-Jung Hsu , Jian-Dong Du
CPC classification number: G06F11/1068 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/3418 , G11C29/52
Abstract: A method used in a flash memory module having a plurality of storage blocks is disclosed. Each storage block can be used as a first block or a second block wherein a cell of the first block is arranged for storing data of 1 bit and a cell of the second block is arranged for storing data of at least 2 bits. The method includes: classifying data to be programmed into a plurality of groups of data; executing error code encoding to generate a corresponding parity check code to store the groups of data and the corresponding parity check code to at least one block of first blocks; and after completing storing the groups of data, performing an internal copy operation upon the groups of data and the corresponding parity check code from the at least one block of the first blocks to at least one second block.
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公开(公告)号：US20180143876A1
公开(公告)日：2018-05-24
申请号：US15874895
申请日：2018-01-19
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Hong-Jung Hsu , Jian-Dong Du
CPC classification number: G06F11/1068 , G11C11/5621 , G11C16/10 , G11C16/26 , G11C29/52
Abstract: A method used for a flash memory module having a plurality of storage blocks each can be used as a first block or a second block includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate a first corresponding parity check code to store the groups of data and the first corresponding parity check code into the flash memory module as first blocks; reading out the groups of data from the first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon the de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon the randomized data to generate a second corresponding parity check code; and storing the randomized data and the second corresponding parity check code into the flash memory module as the second block.
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公开(公告)号：US20180121347A1
公开(公告)日：2018-05-03
申请号：US15859724
申请日：2018-01-01
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Hong-Jung Hsu
CPC classification number: G06F12/0246 , G06F3/0608 , G06F3/061 , G06F3/0629 , G06F11/1004 , G06F12/0804 , G06F2212/1016 , G06F2212/1032 , G06F2212/7203 , G06F2212/7208 , G11C2211/5641
Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
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公开(公告)号：US09858996B2
公开(公告)日：2018-01-02
申请号：US15426070
申请日：2017-02-07
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Hsiao-Te Chang , Wen-Long Wang
CPC classification number: G11C11/5642 , G06F3/0604 , G06F3/0622 , G06F3/0629 , G06F3/0638 , G06F3/0679 , G11C11/5628 , G11C16/08 , G11C16/26
Abstract: A memory access module for performing memory access management of a storage device including a plurality of storage cells includes: sensing means for performing a plurality of sensing operations respectively corresponding to a plurality of different sensing voltages in order to generate a first digital value and a second digital value of a storage cell; processing means for using the first digital value and the second digital value to obtain soft information of a same bit stored in the storage cell; decoding means for using the soft information to perform soft decoding; and controlling means for accessing the storage device. The controlling means includes: storage means for storing a program code; and processing means for executing a program code to control access to the storage device and manage the plurality of storage cells.
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Patent Agency Ranking
公开(公告)号：US20170315908A1
公开(公告)日：2017-11-02
申请号：US15497185
申请日：2017-04-25
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Hong-Jung Hsu
CPC classification number: G06F12/0246 , G06F3/0608 , G06F3/061 , G06F3/0629 , G06F11/1004 , G06F12/0804 , G06F2212/1016 , G06F2212/1032 , G06F2212/7203 , G06F2212/7208 , G11C2211/5641
Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
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87.发明申请公开(公告)号：US20170288699A1
公开(公告)日：2017-10-05
申请号：US15086006
申请日：2016-03-30
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Jian-Dong Du
IPC: H03M13/11
CPC classification number: H03M13/1108 , H03M13/1111 , H03M13/1125 , H03M13/1128 , H03M13/3707 , H03M13/3715 , H03M13/45
Abstract: A method for using a first decoder operating in a hard decision hard decoding mode to generate soft information for a second decoder operating in a hard decision soft decoding mode includes: generating a look-up table (LUT) linking a number of failed check nodes to a log-likelihood ratio (LLR) value; in a first iteration of the first decoder, inputting the number of failed check nodes to the LUT table to generate an LLR value; and outputting the LLR value to the second decoder.
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公开(公告)号：US20170185479A1
公开(公告)日：2017-06-29
申请号：US15423593
申请日：2017-02-03
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang
CPC classification number: G06F11/1068 , G06F11/1012 , G11C11/5642 , G11C16/26 , G11C29/028 , G11C29/52 , G11C2029/0411 , H03M13/1102
Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.
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公开(公告)号：US20170162271A1
公开(公告)日：2017-06-08
申请号：US15439916
申请日：2017-02-22
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang
CPC classification number: G11C16/3431 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/34 , G11C16/3495 , G11C29/00
Abstract: A refresh method for a flash memory includes at least the following steps: performing a write operation to store an input data into a storage space in the flash memory; checking reliability of the storage space with the input data already stored therein; and when the reliability of the storage space meets a predetermined criterion, performing a refresh operation upon the storage space based on the input data. For example, the write operation stores the input data into the storage space through an initial program operation and at least one reprogram operation following the initial program operation; and the refresh operation is an additional reprogram operation applied to the storage space for programming the input data recovered from the storage space into original storage locations in the storage space.
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公开(公告)号：US09666294B2
公开(公告)日：2017-05-30
申请号：US15170952
申请日：2016-06-02
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang
CPC classification number: G11C16/26 , G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F11/1068 , G06F11/1072 , G11C11/5642 , G11C16/0475 , G11C16/0483 , G11C16/3427 , G11C29/52 , G11C2211/5644 , G11C2211/5648 , H03M13/152
Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.
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