公开(公告)号：US09589838B2

公开(公告)日：2017-03-07

申请号：US14752402

申请日：2015-06-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sung-Li Wang ,  Ding-Kang Shih ,  Chin-Hsiang Lin ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L21/336 ,  H01L21/768 ,  H01L29/06 ,  H01L23/485 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/76856 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/285 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76888 ,  H01L23/485 ,  H01L29/0684 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and a metal layer filling a coated opening of the dielectric layer.

Abstract translation: 本发明涉及半导体器件的接触结构。 用于半导体器件的接触结构的示例性结构包括：基底，其包括主表面和主表面下方的沟槽; 填充沟槽的应变材料，其中应变材料的晶格常数不同于衬底的晶格常数; 在所述应变材料上具有开口的层间介电层（ILD）层，其中所述开口包括电介质侧壁和应变材料底部; 涂覆所述开口的侧壁和底部的电介质层，其中所述电介质层具有1nm至10nm的厚度; 以及填充介电层的涂覆开口的金属层。

公开(公告)号：US09366969B2

公开(公告)日：2016-06-14

申请号：US13923968

申请日：2013-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Chu Liu ,  Kuei Shun Chen ,  Norman Chen ,  Vencent Chang ,  Chin-Hsiang Lin

IPC: G03B27/54 ,  G03F7/20

CPC classification number: G03F7/70058 ,  G03F7/70125 ,  G03F7/70425

Abstract: System and method for enhancing optical lithography methodology for hole patterning in semiconductor fabrication are described. In one embodiment, a photolithography system comprises an illumination system for conditioning light from a light source, the illumination system producing a three-pore illumination pattern; a reticle comprising at least a portion of a pattern to be imaged onto a substrate, wherein the three-pore illumination pattern produced by the illumination system is projected through the reticle; and a projection lens disposed between the reticle and the substrate.

公开(公告)号：US20160027708A1

公开(公告)日：2016-01-28

申请号：US14873480

申请日：2015-10-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Tien Chang ,  Sunny Wu ,  Jo Fei Wang ,  Jong-I Mou ,  Chin-Hsiang Lin

IPC: H01L21/66 ,  H01L21/324 ,  H01L21/67

CPC classification number: H01L22/26 ,  H01L21/324 ,  H01L21/67115 ,  H01L21/67248 ,  H05B1/0233

Abstract: An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer processing chamber. The apparatus further includes radiant heating elements disposed in different zones and operable to heat different portions of a wafer located within the wafer processing chamber. The apparatus further includes sensors disposed outside the wafer processing chamber and operable to monitor energy from the radiant heating elements disposed in the different zones. The apparatus further includes a computer configured to utilize the sensors to characterize the radiant heating elements disposed in the different zones and to provide a calibration for the radiant heating elements disposed in the different zones such that a substantially uniform temperature profile is maintained across a surface of the wafer.

Abstract translation: 公开了一种装置，系统和方法。 示例性装置包括晶片处理室。 该设备还包括设置在不同区域中的辐射加热元件，其可操作以加热位于晶片处理室内的晶片的不同部分。 该装置还包括设置在晶片处理室外部的传感器，其可操作以监测来自设置在不同区域中的辐射加热元件的能量。 该装置还包括计算机，其被配置为利用传感器来表征设置在不同区域中的辐射加热元件，并且为放置在不同区域中的辐射加热元件提供校准，使得基本上均匀的温度分布保持在 晶圆。

公开(公告)号：US09214556B2

公开(公告)日：2015-12-15

申请号：US13963887

申请日：2013-08-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Clement Hsingjen Wann ,  Sey-Ping Sun ,  Ling-Yen Yeh ,  Chi-Yuan Shih ,  Li-Chi Yu ,  Chun Hsiung Tsai ,  Chin-Hsiang Lin ,  Neng-Kuo Chen ,  Meng-Chun Chang ,  Ta-Chun Ma ,  Gin-Chen Huang ,  Yen-Chun Huang

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/28518 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes growing an epitaxy semiconductor region at a major surface of a wafer. The epitaxy semiconductor region has an upward facing facet facing upwardly and a downward facing facet facing downwardly. The method further includes forming a first metal silicide layer contacting the upward facing facet, and forming a second metal silicide layer contacting the downward facing facet. The first metal silicide layer and the second metal silicide layer comprise different metals.

Abstract translation: 一种方法包括在晶片的主表面上生长外延半导体区域。 外延半导体区域具有朝上的面向上的朝向小面和朝下的向下的小面。 该方法还包括形成与向上朝向的小面接触的第一金属硅化物层，以及形成接触向下的小面的第二金属硅化物层。 第一金属硅化物层和第二金属硅化物层包括不同的金属。

公开(公告)号：US09105490B2

公开(公告)日：2015-08-11

申请号：US13629109

申请日：2012-09-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sung-Li Wang ,  Ding-Kang Shih ,  Chin-Hsiang Lin ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L29/94 ,  H01L29/06 ,  H01L21/36 ,  H01L23/485 ,  H01L21/768 ,  H01L29/417 ,  H01L21/02

CPC classification number: H01L21/76856 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/285 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76888 ,  H01L23/485 ,  H01L29/0684 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and a metal layer filling a coated opening of the dielectric layer.

Abstract translation: 本发明涉及半导体器件的接触结构。 用于半导体器件的接触结构的示例性结构包括：基底，其包括主表面和主表面下方的沟槽; 填充沟槽的应变材料，其中应变材料的晶格常数不同于衬底的晶格常数; 在所述应变材料上具有开口的层间介电层（ILD）层，其中所述开口包括电介质侧壁和应变材料底部; 涂覆所述开口的侧壁和底部的电介质层，其中所述电介质层具有1nm至10nm的厚度; 以及填充介电层的涂覆开口的金属层。

公开(公告)号：US20150221751A1

公开(公告)日：2015-08-06

申请号：US14688120

申请日：2015-04-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sey-Ping Sun ,  Sung-Li Wang ,  Chin-Hsiang Lin ,  Neng-Kuo Chen ,  Clement Hsingjen Wann

IPC: H01L29/66 ,  H01L21/324 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L21/324 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/785

Abstract: A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate, fins on the substrate, isolation regions on sides of the fins and dummy gate stacks on the substrate including wrapping a portion of the fin, which is referred to as a gate channel region. The dummy gate stacks is removed to form a gate trench and a gate dielectric layer is deposited in the gate trench. A metal stressor layer (MSL) is conformably deposited on the gate dielectric layer. A capping layer is deposited on the MSL. A thermal treatment is applied to the MSL to achieve a volume expansion. Then the capping layer is removed and a metal gate (MG) is formed on the MSL.

Abstract translation: 通过首先接收FinFET前体来制造FinFET器件。 FinFET前体包括衬底，衬底上的翅片，翅片侧面上的隔离区域和衬底上的伪栅极叠层，包括包裹鳍片的一部分，其被称为栅极沟道区域。 去除虚拟栅极堆叠以形成栅极沟槽，并且栅极介电层沉积在栅极沟槽中。 金属应力层（MSL）被顺应地沉积在栅极介电层上。 覆盖层沉积在MSL上。 对MSL进行热处理以实现体积膨胀。 然后去除覆盖层，并在MSL上形成金属栅极（MG）。

公开(公告)号：US20150221561A1

公开(公告)日：2015-08-06

申请号：US14684953

申请日：2015-04-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Lin Chang ,  Chih-Hong Hwang ,  Nai-Han Cheng ,  Chi-Ming Yang ,  Chin-Hsiang Lin

IPC: H01L21/66 ,  H01L21/265

CPC classification number: H01L22/10 ,  H01J37/244 ,  H01J37/3171 ,  H01J2237/24542 ,  H01J2237/30455 ,  H01J2237/31703 ,  H01L21/265

Abstract: A method comprises placing a wafer and a ring-shaped beam profiler on a wafer holder, wherein the ring-shaped beam profiler is adjacent to the wafer, moving a first sensor and a second sensor simultaneously with the wafer holder, receiving a first sensed signal and a second sensed signal from the first sensor and the second sensor respectively and adjusting an ion beam generated by an ion beam generator based upon the first sensed signal and the second sensed signal.

Abstract translation: 一种方法包括将晶片和环形光束轮廓仪放置在晶片保持器上，其中环形光束轮廓仪邻近晶片，与晶片保持器同时移动第一传感器和第二传感器，接收第一感测信号 以及分别来自第一传感器和第二传感器的第二检测信号，并且基于第一感测信号和第二感测信号调整由离子束发生器产生的离子束。

公开(公告)号：US09099494B2

公开(公告)日：2015-08-04

申请号：US14609082

申请日：2015-01-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sung-Li Wang ,  Ding-Kang Shih ,  Chin-Hsiang Lin ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L21/285 ,  H01L21/60 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762

CPC classification number: H01L29/66636 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02614 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28525 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/41758 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7378 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer.

Abstract translation: 本发明涉及半导体器件的接触结构。 用于半导体器件的接触结构的示例性结构包括：基底，其包括主表面和主表面下方的沟槽; 填充沟槽的应变材料，其中应变材料的晶格常数不同于衬底的晶格常数; 在所述应变材料上具有开口的层间介电层（ILD）层，其中所述开口包括电介质侧壁和应变材料底部; 在开口的侧壁和底部上的半导体层; 半导体层上的介电层; 以及填充介电层的开口的金属层。

公开(公告)号：US20150107634A1

公开(公告)日：2015-04-23

申请号：US14581509

申请日：2014-12-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ying-Hsueh Chang Chien ,  Chin-Hsiang Lin ,  Chi-Ming Yang ,  Ming-Hsi Yeh ,  Shao-Yen Ku

IPC: B08B3/12 ,  B08B3/02

CPC classification number: B08B3/12 ,  B08B3/02 ,  H01L21/67028 ,  H01L21/6704

Abstract: A movable wafer probe may include: an immersion hood including a top body portion and a bottom foot portion, the top body portion having first inner sidewalls surrounding a top opening, the bottom foot portion having second inner sidewalls surrounding a bottom opening; a transducer disposed above the bottom opening and within the top opening, the transducer spaced apart from the first inner sidewalls of the top body portion by a first spacing, the first spacing forming a fluid exhaust port; and a fluid input port extending through the transducer, a bottom end of the fluid input port opening to the bottom opening

Abstract translation: 可移动晶片探针可以包括：浸没罩，包括顶部主体部分和底部底部部分，顶部本体部分具有围绕顶部开口的第一内侧壁，底部底部部分具有围绕底部开口的第二内侧壁; 设置在所述底部开口上方且在所述顶部开口内的换能器，所述换能器与所述顶部主体部分的所述第一内侧壁间隔开第一间隔，所述第一间隔形成流体排出口; 以及延伸穿过所述换能器的流体输入端口，所述流体输入端口的底端通向所述底部开口

公开(公告)号：US09006676B2

公开(公告)日：2015-04-14

申请号：US13918731

申请日：2013-06-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Lin Chang ,  Chih-Hong Hwang ,  Nai-Han Cheng ,  Chi-Ming Yang ,  Chin-Hsiang Lin

IPC: H01L21/66 ,  H01J37/244 ,  H01J37/317

CPC classification number: H01L22/10 ,  H01J37/244 ,  H01J37/3171 ,  H01J2237/24542 ,  H01J2237/30455 ,  H01J2237/31703 ,  H01L21/265

Abstract: An apparatus for monitoring an ion distribution of a wafer comprises a first sensor and a sensor. The first sensor, the second sensor and the wafer are placed in an effective range of a uniform ion implantation current profile. A controller determines the ion dose of each region of the wafer based upon the detected signal from the first sensor and the second sensor. In addition, the controller adjusts the scanning frequency of an ion beam or the movement speed of the wafer to achieve a uniform ion distribution on the wafer.

Abstract translation: 用于监测晶片的离子分布的装置包括第一传感器和传感器。 将第一传感器，第二传感器和晶片放置在均匀离子注入电流分布的有效范围内。 控制器基于来自第一传感器和第二传感器的检测信号来确定晶片的每个区域的离子剂量。 此外，控制器调节离子束的扫描频率或晶片的移动速度，以在晶片上实现均匀的离子分布。