公开(公告)号：US20160322263A1

公开(公告)日：2016-11-03

申请号：US15204428

申请日：2016-07-07

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Amitava Chatterjee

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/10 ,  H01L21/265 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/105 ,  H01L29/42364

Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.

公开(公告)号：US09240465B2

公开(公告)日：2016-01-19

申请号：US14821085

申请日：2015-08-07

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L21/324 ,  H01L21/225 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L29/66712 ,  H01L21/225 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/42368 ,  H01L29/66674 ,  H01L29/66734 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7813

Abstract: A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the vertical drift region by at least one instance of the deep trench structures. Dopants are implanted into the vertical drain contact regions and the semiconductor device is annealed so that the implanted dopants diffuse proximate to a bottom of the deep trench structures. The vertical drain contact regions make electrical contact to the proximate vertical drift region at the bottom of the intervening deep trench structure. At least one gate, body region and source region are formed above the drift region at, or proximate to, a top surface of a substrate of the semiconductor device. The deep trench structures are spaced so as to form RESURF regions for the drift region.

公开(公告)号：US09202692B2

公开(公告)日：2015-12-01

申请号：US14572936

申请日：2014-12-17

Applicant: Texas Instruments Incorporated

Inventor： Philip Leland Hower ,  Sameer Pendharkar ,  Marie Denison

IPC: H01L29/66 ,  H01L21/225 ,  H01L27/098 ,  H01L21/8232 ,  H01L29/06 ,  H01L21/266

CPC classification number: H01L29/808 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/32 ,  H01L21/8232 ,  H01L27/098 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0843 ,  H01L29/1058 ,  H01L29/36 ,  H01L29/66901

Abstract: An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer.

Abstract translation: 一种集成电路和方法，其具有具有埋入漂移层的JFET和掩埋沟道，其中通过分段注入区域注入形成掩埋沟道，使得掩埋沟道的掺杂密度在掺杂密度的25％至50％之间 的埋层漂移层。

公开(公告)号：US09159725B2

公开(公告)日：2015-10-13

申请号：US13946415

申请日：2013-07-19

Applicant: Texas Instruments Incorporated

Inventor： Hassan P. Forghani-Zadeh ,  Sameer Pendharkar

IPC: H01L31/0256 ,  H01L27/088 ,  H01L29/20 ,  H01L21/8236 ,  H01L29/778

CPC classification number: H01L27/0883 ,  H01L21/8236 ,  H01L29/2003 ,  H01L29/7787 ,  H03K17/102 ,  H03K17/567 ,  H03K2017/6875

Abstract: A semiconductor device includes a depletion mode GaN FET cascoded with an enhancement mode NMOS transistor. A gate of the GaN FET is electrically coupled to a source of the NMOS transistor through a gate network. The gate network controls at least one of a turn-on time and a turn-off time of the GaN FET. The gate network may be controlled by an input signal to a gate of the NMOS transistor.

Abstract translation: 半导体器件包括与增强型NMOS晶体管级联的耗尽型GaN FET。 GaN FET的栅极通过栅极网络电耦合到NMOS晶体管的源极。 栅极网络控制GaN FET的导通时间和关断时间中的至少一个。 栅极网络可以由到NMOS晶体管的栅极的输入信号来控制。

公开(公告)号：US09136368B2

公开(公告)日：2015-09-15

申请号：US14044909

申请日：2013-10-03

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/66712 ,  H01L21/225 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/42368 ,  H01L29/66674 ,  H01L29/66734 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7813

Abstract: A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the vertical drift region by at least one instance of the deep trench structures. Dopants are implanted into the vertical drain contact regions and the semiconductor device is annealed so that the implanted dopants diffuse proximate to a bottom of the deep trench structures. The vertical drain contact regions make electrical contact to the proximate vertical drift region at the bottom of the intervening deep trench structure. At least one gate, body region and source region are formed above the drift region at, or proximate to, a top surface of a substrate of the semiconductor device. The deep trench structures are spaced so as to form RESURF regions for the drift region.

Abstract translation: 半导体器件具有深沟槽结构的垂直漏极扩展MOS晶体管，以限定垂直漂移区域和至少一个垂直漏极接触区域，其通过深沟槽结构的至少一个实例与垂直漂移区域分离。 将掺杂剂注入到垂直漏极接触区域中，并且半导体器件被退火，使得注入的掺杂剂在深沟槽结构的底部附近扩散。 垂直漏极接触区域在中间深沟槽结构的底部处与邻近的垂直漂移区域电接触。 至少一个栅极，主体区域和源极区域形成在半导体器件的衬底的顶表面处或附近的漂移区域上方。 深沟槽结构被间隔开以形成漂移区域的RESURF区域。

公开(公告)号：US09117691B2

公开(公告)日：2015-08-25

申请号：US14101442

申请日：2013-12-10

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Sameer Pendharkar

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L27/092 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823456 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/7835

Abstract: An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the gate, but exposes a channel region to the well dopants. A thermal drive step diffuses the implanted well dopants across the two diluted regions to form a continuous well with lower doping densities in the two diluted regions. Source/drain regions are formed adjacent to and underlapping the gate by implanting source/drain dopants into the substrate adjacent to the gate using the gate as a blocking layer and subsequently annealing the substrate so that the implanted source/drain dopants provide a desired extent of underlap of the source/drain regions under the gate. Drain extension dopants and halo dopants are not implanted into the substrate adjacent to the gate.

Abstract translation: 包含模拟MOS晶体管的集成电路具有用于阱的注入掩模，该掩模从栅极边缘处的两个稀释区域阻挡良好的掺杂剂，但是将沟道区域暴露于阱掺杂剂。 热驱动步骤将注入的阱掺杂物扩散到两个稀释区域上以在两个稀释区域中形成具有较低掺杂密度的连续阱。 通过使用栅极作为阻挡层将源极/漏极掺杂剂注入邻近栅极的衬底中，形成栅/漏区邻近并且使其重叠，随后使衬底退火，使得注入的源极/漏极掺杂剂提供期望的程度 栅极下的源极/漏极区的叠加。 漏极延伸掺杂剂和卤素掺杂剂不会被注入到与栅极相邻的衬底中。

公开(公告)号：US09117687B2

公开(公告)日：2015-08-25

申请号：US13663015

申请日：2012-10-29

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar ,  Seetharaman Sridhar ,  Jarvis Jacobs

IPC: H01L21/8238 ,  H01L29/06 ,  H01L21/761 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/761 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0883 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

Abstract translation: 包含在低电压范围内工作的第一多个MOS晶体管的集成电路和在中间电压范围内工作的第二多个MOS晶体管也可以包括高电压MOS晶体管，其操作在明显高于 低电压和中等电压范围，例如20至30伏特。 高压MOS晶体管具有闭环配置，其中漏极区域被栅极包围，栅极又被源极区域包围，使得栅极不与场氧化物重叠。 集成电路可以包括高压MOS晶体管的n沟道版本和/或高压MOS晶体管的p沟道版本。 n沟道版本和p沟道版本的注入区域与第一和第二多个MOS晶体管中的注入区域同时形成。

公开(公告)号：US09064726B2

公开(公告)日：2015-06-23

申请号：US13789477

申请日：2013-03-07

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Amitava Chatterjee

IPC: H01L21/20 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/105 ,  H01L29/42364

Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.

Abstract translation: 第一类型的杂质原子通过栅极和薄栅极电介质注入到在沟道区的中间点处基本上仅具有第一类型的杂质原子的沟道区，以增加第一类杂质的平均掺杂浓度 通道区域中的原子来调节晶体管的阈值电压。

公开(公告)号：US09054071B2

公开(公告)日：2015-06-09

申请号：US14450784

申请日：2014-08-04

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni

IPC: H01L21/76 ,  H01L29/40 ,  H01L21/311 ,  H01L29/417 ,  H01L29/66 ,  H01L29/812 ,  H01L29/20

CPC classification number: H01L29/404 ,  H01L21/31144 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66871 ,  H01L29/78 ,  H01L29/812

Abstract: A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate.

Abstract translation: 半导体器件在至少三个连续区域上形成有台阶式场板，其中在阶梯式场板下的总电介质厚度与先前区域相比在每个区域中至少为10％以上。 各区域的总电介质厚度均匀。 阶梯式场板形成在至少两个电介质层上，至少两个电介质层至少形成一个电介质层，使得图案化的电介质层的至少一部分在阶梯式场板的一个或多个区域中被去除。

公开(公告)号：US09035318B2

公开(公告)日：2015-05-19

申请号：US13886378

申请日：2013-05-03

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni

IPC: H01L29/15 ,  H01L27/02 ,  H01L29/20 ,  H01L29/267 ,  H01L29/778 ,  H01L29/10 ,  H01L29/78 ,  H01L49/02

CPC classification number: H01L29/7787 ,  H01L21/8232 ,  H01L21/8252 ,  H01L27/0255 ,  H01L27/0605 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/7833

Abstract: A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.

Abstract translation: 半导体器件包括具有电耦合到GaN FET的漏极节点并且与降压部件串联耦合的过压钳位部件的GaN FET。 降压组件电耦合到为GaN FET提供截止状态偏置的端子。 当GaN FET的漏极节点处的电压小于GaN FET的击穿电压时，过电压钳位部件导通无效电流，并且当电压上升到高于安全电压限度时，导通显着的电流。 降压部件被配置为提供随着来自过电压钳位部件的电流增加而增加的电压降。 半导体器件被配置为当跨越降压元件的电压降达到阈值时接通GaN FET。