利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

119 条记录 (耗时 0.032 秒)

    Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage
    83.
    发明申请
    Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage 失效
    使用保护层制造鳍状场效应晶体管以减少蚀刻损伤的方法

    公开(公告)号：US20050019993A1

    公开(公告)日：2005-01-27

    申请号：US10869764

    申请日：2004-06-16

    申请人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

    发明人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

    IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L21/00 ,  H01L21/44 ,  H01L21/8242

    CPC分类号： H01L29/7851 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795

    摘要： A method of forming a fin field effect transistor on a semiconductor substrate includes forming a vertical fin protruding from the substrate. A buffer oxide liner is formed on a top surface and on sidewalls of the fin. A trench is then formed on the substrate, where at least a portion of the fin protrudes from a bottom surface of the trench. The trench may be formed by forming a dummy gate on at least a portion of the fin, forming an insulation layer on the fin surrounding the dummy gate, and then removing the dummy gate to expose the at least a portion of the fin, such that the trench is surrounded by the insulation layer. The buffer oxide liner is then removed from the protruding portion of the fin, and a gate is formed in the trench on the protruding portion of the fin.

    摘要翻译： 在半导体衬底上形成鳍状场效应晶体管的方法包括形成从衬底突出的垂直翅片。 缓冲氧化物衬垫形成在翅片的顶表面和侧壁上。 然后在衬底上形成沟槽，其中鳍的至少一部分从沟槽的底表面突出。 可以通过在鳍片的至少一部分上形成伪栅极来形成沟槽，在围绕虚拟栅极的鳍片上形成绝缘层，然后去除伪栅极以暴露鳍片的至少一部分，使得 沟槽被绝缘层包围。 然后从鳍片的突出部分去除缓冲氧化物衬垫，并且在鳍片的突出部分上的沟槽中形成栅极。

    Method and device for forming an STI type isolation in a semiconductor device
    84.
    发明授权
    Method and device for forming an STI type isolation in a semiconductor device 失效
    在半导体器件中形成STI型隔离的方法和装置

    公开(公告)号：US06835996B2

    公开(公告)日：2004-12-28

    申请号：US10684451

    申请日：2003-10-15

    申请人： Chul-Sung Kim ,  Si-Young Choi ,  Jung-Woo Park ,  Jong-Ryol Ryu ,  Byeong-Chan Lee

    发明人： Chul-Sung Kim ,  Si-Young Choi ,  Jung-Woo Park ,  Jong-Ryol Ryu ,  Byeong-Chan Lee

    IPC分类号： H01L2900

    CPC分类号： H01L21/76224

    摘要： A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.

    摘要翻译： 半导体器件中的沟槽隔离及其制造方法包括：在硅衬底中形成具有用于器件隔离的内侧壁的沟槽; 在形成沟槽的内侧壁的硅衬底的表面上形成氧化物层; 向硅衬底提供愈合元件以去除悬挂键; 并用器件隔离层填充沟槽，从而形成沟槽隔离，而不产生悬挂键导致电荷陷阱。

    Methods of forming electrical interconnects on semiconductor substrates
    86.
    发明授权
    Methods of forming electrical interconnects on semiconductor substrates 失效
    在半导体衬底上形成电互连的方法

    公开(公告)号：US5863835A

    公开(公告)日：1999-01-26

    申请号：US906718

    申请日：1997-08-05

    申请人： Bong-Young Yoo ,  Si-Young Choi

    发明人： Bong-Young Yoo ,  Si-Young Choi

    IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/522

    CPC分类号： H01L21/76885 ,  H01L21/76807 ,  H01L23/5226 ,  H01L2924/0002

    摘要： Methods of forming electrical interconnects on semiconductor substrates include the steps of forming a first electrically insulating layer (e.g., silicon dioxide) and then forming a contact hole in the insulating layer to expose a layer underlying the insulating layer. A first electrically conductive region (e.g., W, Ti, Tin, Al) is then formed in the contact hole. A step is then performed to remove a portion of the first electrically insulating layer to define a recess therein which preferably surrounds an upper portion of the first conductive region. A second electrically conductive region (e.g., Al, Cu, W, Ti, Ta and Co) is then formed in the recess. Here, the first conductive region is preferably chosen to have good step coverage capability to fully bury the contact hole and the second conductive region is preferably chosen to have very low resistance even if some degree of step coverage capability is sacrificed. Planarization steps (e.g, CMP, etch-back) may also be performed to define the first conductive region in the contact hole and define the second conductive region in the recess surrounding the first conductive region. Barrier metal layers may also be conformable deposited in the contact hole prior to forming the first conductive region therein and in the recess prior to forming the second conductive region therein.

    摘要翻译： 在半导体衬底上形成电互连的方法包括以下步骤：形成第一电绝缘层（例如二氧化硅），然后在绝缘层中形成接触孔以暴露绝缘层下面的层。 然后在接触孔中形成第一导电区域（例如，W，Ti，Tin，Al）。 然后执行步骤以去除第一电绝缘层的一部分以限定其中优选围绕第一导电区域的上部的凹部。 然后在凹部中形成第二导电区域（例如Al，Cu，W，Ti，Ta和Co）。 这里，优选地选择第一导电区域以具有良好的阶梯覆盖能力以完全埋入接触孔，并且即使牺牲了某种程度的阶梯覆盖能力，优选将第二导电区域选择为具有非常低的电阻。 还可以执行平面化步骤（例如，CMP，回蚀刻）以限定接触孔中的第一导电区域并限定围绕第一导电区域的凹部中的第二导电区域。 阻挡金属层也可以在其中形成第一导电区域之前以及在其中形成第二导电区域之前在凹部中沉积在接触孔中。

    Mask for forming patterns of semiconductor device
    87.
    发明授权
    Mask for forming patterns of semiconductor device 有权
    用于形成半导体器件图案的掩模

    公开(公告)号：US08592104B2

    公开(公告)日：2013-11-26

    申请号：US13224471

    申请日：2011-09-02

    申请人： Yun-Suk Nam ,  Si-Young Choi ,  Yong-Kug Bae

    发明人： Yun-Suk Nam ,  Si-Young Choi ,  Yong-Kug Bae

    IPC分类号： G03F1/70

    CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/36

    摘要： A mask for forming patterns of a semiconductor device is provided. The mask includes first and second main patterns disposed to be spaced apart from each other about a cross point and extending in first and second directions different from each other, a third main pattern disposed spaced apart from the first and second main patterns while being disposed between the first and second main patterns so as to overlap the cross point, and at least one auxiliary pattern spaced apart from the third main pattern in the periphery of a portion of the third main pattern, which is not adjacent with the first and second main patterns.

    摘要翻译： 提供了用于形成半导体器件的图案的掩模。 掩模包括第一和第二主图案，其布置成围绕交叉点彼此间隔开并且在彼此不同的第一和第二方向上延伸;第三主图案，布置在与第一和第二主图案间隔开的同时设置在 所述第一和第二主图案与所述交叉点重叠，以及与所述第三主图案的不相邻的所述第三主图案的一部分的周边中的与所述第三主图案间隔开的至少一个辅助图案， 。

    Methods of fabricating silicon oxide layers using inorganic silicon precursors and methods of fabricating semiconductor devices including the same
    89.
    发明授权
    Methods of fabricating silicon oxide layers using inorganic silicon precursors and methods of fabricating semiconductor devices including the same 失效
    使用无机硅前体制造氧化硅层的方法和制造包括其的半导体器件的方法

    公开(公告)号：US08227357B2

    公开(公告)日：2012-07-24

    申请号：US12730406

    申请日：2010-03-24

    申请人： In-Sun Yi ,  Ki-Hyun Hwang ,  Jin-Tae Noh ,  Jae-Young Ahn ,  Si-Young Choi

    发明人： In-Sun Yi ,  Ki-Hyun Hwang ,  Jin-Tae Noh ,  Jae-Young Ahn ,  Si-Young Choi

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/28273 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02219 ,  H01L21/0228 ,  H01L21/28282 ,  H01L21/3185 ,  H01L27/11521 ,  H01L27/11568

    摘要： Methods of fabricating a silicon oxide layer using an inorganic silicon precursor and methods of fabricating a semiconductor device using the same are provided. The methods of fabricating a semiconductor device include forming a tunnel insulating layer and a charge storage layer on a substrate; forming a dielectric layer structure on the charge storage layer using an atomic layer deposition (ALD) method, the dielectric layer structure including a first dielectric layer formed of silicon oxide, a second dielectric layer on the first dielectric layer formed of a material different from the material forming the first dielectric layer, and a third dielectric layer formed of the silicon oxide on the second dielectric layer; and forming a control gate on the dielectric layer structure. The first and third dielectric layers formed of the silicon oxide are formed using a first gas including an inorganic silicon precursor, a second gas including hydrogen gas or a hydrogen component, and a third gas including an oxide gas.

    摘要翻译： 提供了使用无机硅前体制造氧化硅层的方法和使用其制造半导体器件的方法。 制造半导体器件的方法包括在衬底上形成隧道绝缘层和电荷存储层; 使用原子层沉积（ALD）方法在所述电荷存储层上形成电介质层结构，所述电介质层结构包括由氧化硅形成的第一电介质层，所述第一电介质层上的第二电介质层由不同于 形成第一电介质层的材料和由第二电介质层上的氧化硅形成的第三电介质层; 以及在介电层结构上形成控制栅极。 由氧化硅形成的第一和第三电介质层使用包括无机硅前体的第一气体，包括氢气或氢组分的第二气体和包括氧化物气体的第三气体形成。

    Mask for Forming Patterns of Semiconductor Device
    90.
    发明申请
    Mask for Forming Patterns of Semiconductor Device 有权
    半导体器件形成掩模

    公开(公告)号：US20120058420A1

    公开(公告)日：2012-03-08

    申请号：US13224471

    申请日：2011-09-02

    申请人： Yun-Suk Nam ,  Si-Young Choi ,  Yong-Kug Bae

    发明人： Yun-Suk Nam ,  Si-Young Choi ,  Yong-Kug Bae

    IPC分类号： G03F1/00

    CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/36

    摘要： A mask for forming patterns of a semiconductor device is provided. The mask includes first and second main patterns disposed to be spaced apart from each other about a cross point and extending in first and second directions different from each other, a third main pattern disposed spaced apart from the first and second main patterns while being disposed between the first and second main patterns so as to overlap the cross point, and at least one auxiliary pattern spaced apart from the third main pattern in the periphery of a portion of the third main pattern, which is not adjacent with the first and second main patterns.

    摘要翻译： 提供了用于形成半导体器件的图案的掩模。 掩模包括第一和第二主图案，其布置成围绕交叉点彼此间隔开并且在彼此不同的第一和第二方向上延伸;第三主图案，布置在与第一和第二主图案间隔开的同时设置在 所述第一和第二主图案与所述交叉点重叠，以及与所述第三主图案的不相邻的所述第三主图案的一部分的周边中的与所述第三主图案间隔开的至少一个辅助图案， 。