公开(公告)号：US20200052131A1

公开(公告)日：2020-02-13

申请号：US16598750

申请日：2019-10-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng Chen ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Carlos H. Diaz

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.

公开(公告)号：US20190109204A1

公开(公告)日：2019-04-11

申请号：US16201523

申请日：2018-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Wei-Sheng Yun ,  I-Sheng Chen ,  Shao-Ming Yu ,  Tzu-Chiang Chen ,  Chih Chieh Yeh

IPC: H01L29/51 ,  H01L21/8238 ,  H01L29/165 ,  H01L27/092

Abstract: A method includes providing a substrate; forming a first structure over the substrate, the first structure including a first gate trench and a first channel exposed in the first gate trench; forming a second structure over the substrate, the second structure including a second gate trench and a second channel exposed in the second gate trench; depositing a gate dielectric layer covering surfaces of the first and second channels exposed in the respective first and second gate trenches; recessing the gate dielectric layer in the second gate trench to be lower than the gate dielectric layer in the first gate trench; and forming a gate electrode layer over the gate dielectric layer in the first and second gate trenches.

公开(公告)号：US20240105515A1

公开(公告)日：2024-03-28

申请号：US18521045

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Tzu-Ang Chao ,  Chun-Chieh Lu ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10K10/46 ,  H10K71/12 ,  H10K85/20

CPC classification number: H01L21/823412 ,  H01L21/02568 ,  H01L21/02603 ,  H01L21/02606 ,  H01L21/0262 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/78696 ,  H10K10/464 ,  H10K10/474 ,  H10K10/484 ,  H10K10/486 ,  H10K71/12 ,  H10K85/221

Abstract: A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.

公开(公告)号：US20230378334A1

公开(公告)日：2023-11-23

申请号：US18364964

申请日：2023-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Tzu Ang Chao ,  Chao-Ching Cheng ,  Lain-Jong Li

IPC: H01L29/76 ,  H01L27/092 ,  H01L29/24 ,  H01L29/417 ,  H01L29/49 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/4757 ,  H01L21/8256 ,  H01L29/66 ,  H01L23/31 ,  H10K10/84 ,  H10K10/88 ,  H10K10/46 ,  H10K19/10 ,  H10K85/20

CPC classification number: H01L29/7606 ,  H01L27/092 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/45 ,  H01L29/78696 ,  H01L21/02568 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/47576 ,  H01L21/8256 ,  H01L29/66969 ,  H01L23/3171 ,  H10K10/84 ,  H10K10/88 ,  H10K10/466 ,  H10K10/484 ,  H10K19/10 ,  H10K85/221

Abstract: A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the isolation layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.

公开(公告)号：US20220352312A1

公开(公告)日：2022-11-03

申请号：US17813777

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Tzu-Ang Chao ,  Chun-Chieh Lu ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li

IPC: H01L29/06 ,  H01L51/05 ,  H01L51/00 ,  H01L21/02 ,  H01L29/786 ,  H01L29/66 ,  H01L29/24 ,  H01L29/423

Abstract: A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.

公开(公告)号：US11437468B2

公开(公告)日：2022-09-06

申请号：US17120852

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  I-Sheng Chen

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088

Abstract: The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages.

公开(公告)号：US20220165871A1

公开(公告)日：2022-05-26

申请号：US17324893

申请日：2021-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yan Chung ,  Chao-Ching Cheng ,  Chao-Hsin Chien

IPC: H01L29/68 ,  H01L21/02 ,  H01L29/24 ,  H01L29/76 ,  H01L29/786 ,  H01L29/66

Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.

公开(公告)号：US20220140098A1

公开(公告)日：2022-05-05

申请号：US17351622

申请日：2021-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Yi-Tse Hung ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li ,  Jin Cai

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66

Abstract: A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

公开(公告)号：US20220059580A1

公开(公告)日：2022-02-24

申请号：US17000582

申请日：2020-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Jung-Piao Chiu ,  Tzu-Chiang Chen ,  Yu-Sheng Chen

IPC: H01L27/146 ,  H01L45/00

Abstract: Disclosed herein, in some embodiments, is a memory device. The memory device includes a bottom electrode disposed over a substrate and a top electrode disposed over the bottom electrode. An upper surface of the bottom electrode faces away from the substrate. A bottom surface of the top electrode faces the substrate. A data storage layer is arranged between the bottom electrode and the top electrode. At least a portion of the bottom surface of the top electrode does not overlap with any portion of the top surface of the bottom electrode along a first direction parallel to the bottom surface of the top electrode. Furthermore, at least a portion of the top surface of the bottom electrode does not overlap with any portion of the bottom surface of the top electrode along the first direction.

公开(公告)号：US11244866B2

公开(公告)日：2022-02-08

申请号：US16932268

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Tse Hung ,  Chao-Ching Cheng ,  Tse-An Chen ,  Hung-Li Chiang ,  Lain-Jong Li ,  Tzu-Chiang Chen

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/306 ,  H01L21/28 ,  H01L29/06 ,  H01L21/02 ,  B82Y40/00

Abstract: In an embodiment, a device includes: a dielectric fin on a substrate; a low-dimensional layer on the dielectric fin, the low-dimensional layer including a source/drain region and a channel region; a source/drain contact on the source/drain region; and a gate structure on the channel region adjacent the source/drain contact, the gate structure having a first width at a top of the gate structure, a second width at a middle of the gate structure, and a third width at a bottom of the gate structure, the second width being less than each of the first width and the third width.