公开(公告)号：US20250118707A1

公开(公告)日：2025-04-10

申请号：US18482632

申请日：2023-10-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Cheng Chen ,  Chao-Wen Shih ,  Min-Chien Hsiao ,  Kuo-Chiang Ting ,  Yen-Ming Chen

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: An integrated circuit package and the method of forming the same are provided. The integrated circuit package may include a first die, a first gap-fill layer along sidewalls of the first die, a first bonding layer on the first die and the first gap-fill layer, and a first die connector in the first bonding layer. The first die connector may be directly over an interface between the first die and the first gap-fill layer.

公开(公告)号：US20240379521A1

公开(公告)日：2024-11-14

申请号：US18783669

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd

Inventor： Ming-Fa Chen ,  Chin-Shyh Wang ,  Chao-Wen Shih

IPC: H01L23/498 ,  H01L21/762 ,  H01L21/768

Abstract: A method includes etching a substrate to form an opening, depositing a first dielectric liner extending into the opening, and depositing a second dielectric liner over the first dielectric liner. The second dielectric liner extends into the opening. A conductive material is filled into the opening. The method further includes performing a first planarization process to planarize the conductive material so that a portion of the conductive material in the opening forms a through-via, performing a backside grinding process on the substrate until the through-via is revealed from a backside of the substrate, and forming a conductive feature on the backside of the substrate. The conductive feature is electrically connected to the through-via.

公开(公告)号：US20240379439A1

公开(公告)日：2024-11-14

申请号：US18781604

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Tzuan-Horng Liu ,  Chao-Wen Shih

IPC: H01L21/768 ,  H01L21/3065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: An embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein, patterning the first interconnect structure to form a first opening, coating the first opening with a barrier layer, etching a second opening through the barrier layer and the exposed portion of the first substrate, depositing a liner in the first opening and the second opening, filling the first opening and the second opening with a conductive material, and thinning the first substrate to expose a portion of the conductive material in the second opening, the conductive material extending through the first interconnect structure and the first substrate forming a through substrate via.

公开(公告)号：US20240375236A1

公开(公告)日：2024-11-14

申请号：US18783920

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Wei Chang ,  Ming-Fa Chen ,  Chao-Wen Shih ,  Ting-Chu Ko

IPC: B24B7/22 ,  B24B37/04 ,  B24B37/08 ,  B24B49/12

Abstract: A method includes bonding a first package component on a composite carrier, and performing a first polishing process on the composite carrier to remove a base carrier of the composite carrier. The first polishing process stops on a first layer of the composite carrier. A second polishing process is performed to remove the first layer of the composite carrier. The second polishing process stops on a second layer of the composite carrier. A third polishing process is performed to remove a plurality of layers in the composite carrier. The plurality of layers include the second layer, and the third polishing process stops on a dielectric layer in the first package component.

公开(公告)号：US20240355782A1

公开(公告)日：2024-10-24

申请号：US18756525

申请日：2024-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Tzuan-Horng Liu ,  Chao-Wen Shih ,  Sung-Feng Yeh ,  Nien-Fang Wu

IPC: H01L25/065 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/66 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/544 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/31053 ,  H01L21/56 ,  H01L21/6836 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/544 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L22/32 ,  H01L24/29 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2224/27616 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/8313 ,  H01L2224/83896 ,  H01L2224/92244 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06586

Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

公开(公告)号：US12057439B2

公开(公告)日：2024-08-06

申请号：US17984379

申请日：2022-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Tzuan-Horng Liu ,  Chao-Wen Shih ,  Sung-Feng Yeh ,  Nien-Fang Wu

IPC: H01L25/065 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/544 ,  H01L25/00 ,  H01L21/66

CPC classification number: H01L25/0657 ,  H01L21/31053 ,  H01L21/56 ,  H01L21/6836 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/544 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L22/32 ,  H01L24/29 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2224/27616 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/8313 ,  H01L2224/83896 ,  H01L2224/92244 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06586

Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

公开(公告)号：US20240055371A1

公开(公告)日：2024-02-15

申请号：US18151556

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Der-Chyang Yeh ,  Kuo-Chiang Ting ,  Yu-Hsiung Wang ,  Chao-Wen Shih ,  Sung-Feng Yeh ,  Ta Hao Sung ,  Cheng-Wei Huang ,  Yen-Ping Wang ,  Chang-Wen Huang ,  Sheng-Ta Lin ,  Li-Cheng Hu ,  Gao-Long Wu

IPC: H01L23/00 ,  H01L23/58 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L23/585 ,  H01L23/481 ,  H01L23/3178 ,  H01L21/565

Abstract: Embodiments include a crack stopper structure surrounding an embedded integrated circuit die, and the formation thereof. The crack stopper structure may include multiple layers separated by a fill layer. The layers of the crack stopper may include multiple sublayers, some of the sublayers providing adhesion, hardness buffering, and material gradients for transitioning from one layer of the crack stopper structure to another layer of the crack stopper structure.

公开(公告)号：US11894309B2

公开(公告)日：2024-02-06

申请号：US17121140

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Tzuan-Horng Liu ,  Ming-Fa Chen ,  Chao-Wen Shih ,  Sung-Feng Yeh

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L21/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4871 ,  H01L21/565 ,  H01L21/78 ,  H01L22/12 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/19103

Abstract: A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.

公开(公告)号：US11823989B2

公开(公告)日：2023-11-21

申请号：US17135435

申请日：2020-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chin-Shyh Wang ,  Chao-Wen Shih

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/498 ,  H01L21/762

CPC classification number: H01L23/49827 ,  H01L21/7684 ,  H01L21/76224 ,  H01L21/76846

Abstract: A method includes etching a substrate to form an opening, depositing a first dielectric liner extending into the opening, and depositing a second dielectric liner over the first dielectric liner. The second dielectric liner extends into the opening. A conductive material is filled into the opening. The method further includes performing a first planarization process to planarize the conductive material so that a portion of the conductive material in the opening forms a through-via, performing a backside grinding process on the substrate until the through-via is revealed from a backside of the substrate, and forming a conductive feature on the backside of the substrate. The conductive feature is electrically connected to the through-via.

公开(公告)号：US20230067035A1

公开(公告)日：2023-03-02

申请号：US17984379

申请日：2022-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Tzuan-Horng Liu ,  Chao-Wen Shih ,  Sung-Feng Yeh ,  Nien-Fang Wu

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L23/544 ,  H01L23/528 ,  H01L25/00 ,  H01L21/56 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/78 ,  H01L21/683 ,  H01L23/48

Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.